Semiconductor Test Device Using Pass/Fail Data to Skip Passed Memory Blocks
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Solution Overview
Problem
The increasing capacity and miniaturization of semiconductor devices lead to a significant increase in the time and resources required for characteristic evaluation tests, making the testing process inefficient and costly due to the need to repeat tests across numerous memory cell blocks with varying conditions.
Innovation Solution
A semiconductor testing device that generates test commands to exclude memory cell blocks that have passed previous tests from subsequent tests, using a data memory to store test results and selectively target memory cell blocks that failed previous tests, thereby reducing the number of tests needed and optimizing testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same operation is repeated many times in all areas of a semiconductor memory device while changing test parameter values, then the characteristics of memory cells are thoroughly tested, but the testing time increases dramatically
Solution Approach 1:
The patent segments the memory device into multiple function areas and divides the testing process into multiple stages. In each stage, only specific function areas that failed previous tests are tested, rather than repeating tests on all areas. This segmentation allows thorough characteristic evaluation while significantly reducing redundant testing time.
Solution Approach 2:
The patent performs preliminary testing on all function areas with initial test parameter values before conducting subsequent tests. The results of these preliminary tests are stored and used to determine which function areas need further testing. This preliminary action eliminates the need to re-test areas that already passed, thereby reducing overall testing time while maintaining evaluation reliability.
2Productivity
If a new memory is arranged in the semiconductor testing device to store test results for each memory block, then test efficiency is improved, but the device complexity and cost increase
Solution Approach 1:
The patent uses a universal data storage area that serves multiple functions: storing test results from preliminary tests, storing identification information of function areas, and storing test parameter values. This multi-functional storage approach improves test efficiency without requiring separate dedicated memory structures for each function, thereby avoiding increased device complexity.
Solution Approach 2:
The patent creates a simplified data structure in the storage area that copies essential information (function area identification and test results) from the complex memory device structure. This copying approach allows efficient test result management without replicating the full complexity of the memory device's physical structure in the testing device.
3Quantity of substance
If the number of memory cell blocks increases with device capacity, then the device functionality is enhanced, but the number of required tests increases dramatically
Solution Approach 1:
The patent divides the large number of memory cell blocks into multiple function areas and further segments the testing process into stages. In each stage, only a subset of function areas is tested based on previous results. This segmentation allows the device to handle increased memory capacity without proportionally increasing the number of tests required, thereby maintaining testing throughput.
Solution Approach 2:
The patent performs tests on only the necessary portion of function areas in each testing stage rather than testing all areas exhaustively. After preliminary testing identifies passing function areas, subsequent tests focus only on failing areas. This partial action approach allows the device to scale in capacity without a proportional increase in testing requirements.
Data Source
AI summary
A semiconductor testing device includes: a data memory which stores a test program, said test program generating a test command for testing a plurality of functions within one function area of a plurality of function areas of a semiconductor device, said test command being generated for said function area; a first area generation part which generates first data, said first data identifying one function area of said plurality of function areas, said plurality of functions of said one function area being tested; a main control part which generates said test command based on said test program and said first data and transmits said test command to said semiconductor device; a second area generation part which receives a first result, said first result being returned from said semiconductor device based on a first test in accordance with said test command and generates a second result based on said first result, said second result showing a pass or failure of said first test corresponding to said function area; and a third area generation part which generates second data based on said second result and transmits said second data to said first area generation part, said first area generation part generating third data based on said second data, said third data identifying one or more of said plurality of function areas, said one or more of said plurality of function areas being the object of a second test subsequent to said first test.