Semiconductor Test Structure for Layer Alignment Detection
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Solution Overview
Problem
Misalignment of layers during semiconductor device manufacturing can lead to short circuits and device failure, necessitating a method to check layer alignment effectively.
Innovation Solution
A test structure and method are provided to check the alignment of control gate and floating gate layers in semiconductor devices by measuring electrical resistance, with normal alignment resulting in high resistance and abnormal alignment causing low resistance due to bridging, allowing for adjustment of manufacturing parameters to correct misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If layer alignment is not tested during manufacturing, then manufacturing process continues without interruption, but short circuits and device failure occur due to misalignment
Solution Approach 1:
The patent implements layer alignment testing at an intermediate stage during the manufacturing process, before final device completion. By performing the test after forming the first conductive layer and removing exposed portions, the alignment can be verified early, allowing corrective actions to be taken before subsequent processing steps are applied to defective devices.
Solution Approach 2:
The test structure utilizes the device's own conductive layers and geometric features to perform the alignment test. The first conductive layer, second conductive layer, and dielectric layer are configured such that the device structure itself provides the test pathway, eliminating the need for external test equipment or additional test-specific components.
2Measurement precision
If alignment testing is performed, then misalignment can be detected early, but additional processing steps and measurement operations are required
Solution Approach 1:
The test structure serves multiple functions: it acts as both the functional device structure (with first conductive layer, second conductive layer, and dielectric layer) and as the alignment test structure simultaneously. The same layers that form the device also provide the test pathway, allowing alignment verification without requiring separate dedicated test structures.
Solution Approach 2:
The patent utilizes electrical resistance as the indicator of alignment status. When layers are properly aligned, the resistance between contact regions is high (indicating no bridging). When misalignment causes bridging, the resistance drops to low values. This resistance change provides a clear, binary indication of alignment quality.
3Productivity
If misaligned devices are processed further, then manufacturing continues without interruption, but costly subsequent operations are performed on defective devices
Solution Approach 1:
The alignment test is performed at an intermediate stage in the manufacturing process, after forming the first conductive layer and removing exposed portions, but before completing all subsequent processing steps. This timing allows early detection of misalignment, enabling defective devices to be identified and excluded before significant additional processing is applied, thereby conserving manufacturing resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient detection of layer misalignment during manufacturing, improving wafer yield and reducing costly subsequent operations by identifying issues before further processing, thus enhancing the manufacturing process economy.
Implementation Method 1
measuring electrical resistance between contact regions of the first conductive layer
Data Source
AI summary
Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer. Electrical resistance across first conductive layer between first and second end portions of first conductive layer is measured.