Semiconductor Test Structure Across Chip Corners
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Solution Overview
Problem
Conventional semiconductor chip fabrication processes face challenges in efficiently testing chips without damaging components, leading to increased space requirements for test structures, which limits the number of chips that can be formed on a wafer and results in stress-induced defects during dicing.
Innovation Solution
A method of forming test structures by extending them across multiple corner areas of semiconductor chips, allowing for larger and more representative test structures to be formed without occupying additional space, thereby reducing the need for 'knockout' areas and mitigating stress-induced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test structures are formed in knockout areas on each chip, then testing can be performed without damaging chip components, but the wafer space required for test structures increases, limiting the number of chips that can be formed on the wafer
Solution Approach 1:
The patent merges test structures across multiple chips by forming continuous test structures that extend through scribe lanes to connect adjacent chips. This consolidation allows a single test structure to serve multiple chips simultaneously, reducing the total wafer space required for testing while maintaining comprehensive testing capability across all chips.
Solution Approach 2:
The patent transitions from forming test structures within individual chip boundaries to extending test structures across chip boundaries into the scribe lanes. This dimensional extension allows test structures to span multiple chips, effectively utilizing the previously wasted scribe lane space and reducing the overall footprint per chip.
2Reliability
If scribe lanes are made wider to allow for dicing without damaging active chip areas, then chip protection during dicing is improved, but the available wafer space for forming chips is reduced
Solution Approach 1:
The patent combines the protective function of wide scribe lanes with the testing function by forming continuous test structures that extend through the scribe lanes. This dual-purpose approach maintains the necessary scribe lane width for chip protection during dicing while utilizing the same space for testing, thereby maximizing wafer space utilization.
3Reliability
If chip corners are left vacant to avoid stress-induced defects during dicing, then defect formation is reduced, but the usable chip area is decreased
Solution Approach 1:
The patent places test structures in the corner regions that would otherwise be vacant, merging the stress-relief function of corner vacancies with the testing function. By forming test structures in these corner areas and extending them through scribe lanes, the patent utilizes previously wasted corner space without compromising the stress-relief benefit during dicing.
Data Source
AI summary
A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.