Semiconductor Test Structure for ILD Void and Contact Resistance
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Solution Overview
Problem
In semiconductor manufacturing, the formation of contact levels with high aspect ratios and strained dielectric materials leads to compatibility issues with gap filling and patterning, resulting in irregularities and significant yield losses due to the incompatibility of high stress levels and gap filling capabilities in densely packed device areas.
Innovation Solution
Implementing a test structure with chain-like interconnect elements and a comb-like conductive line structure within the semiconductor device to assess leakage currents and contact resistivity efficiently, allowing for a high density of measurement data collection in a compact area, similar to critical device regions, and reducing the need for additional test structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high stress levels are applied to dielectric materials to induce strain in transistor channels, then transistor performance is improved, but gap filling capabilities deteriorate leading to deposition irregularities
Solution Approach 1:
The dielectric material system is segmented into multiple layers with different stress characteristics. A first dielectric layer provides compressive stress to induce strain in the transistor channel for improved performance, while a second dielectric layer provides tensile stress to counterbalance the compression and enable proper gap filling during deposition processes.
Solution Approach 2:
The patent uses a composite dielectric material system consisting of at least two different dielectric layers with opposing stress properties. This composite structure allows simultaneous achievement of strain-induced performance enhancement and manufacturing process compatibility by combining materials with complementary characteristics.
2Quantity of substance
If contact openings with high aspect ratios are formed to connect densely packed circuit elements, then connection density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent addresses the high aspect ratio problem by transitioning from a single-layer contact approach to a multi-layer interconnect structure. Contact openings are distributed across multiple dielectric layers, allowing connections to be established through vertical stacking rather than requiring single deep holes, thereby reducing the effective aspect ratio of individual contact openings.
3Measurement precision
If additional test structures are implemented to monitor contact levels and leakage paths, then measurement capability is improved, but device area increases
Solution Approach 1:
The interconnect chain structure serves multiple functions simultaneously: it provides actual electrical interconnection between circuit elements and acts as an integrated test structure for monitoring contact resistivity and leakage currents. This multi-functionality eliminates the need for separate dedicated test structures, saving device area while maintaining comprehensive monitoring capability.
Solution Approach 2:
The patent merges the functional interconnect structure with the test structure into a single integrated chain structure. The same conductive pathways used for signal transmission also serve as measurement paths for electrical testing, combining utility and diagnostics into one unified structure.
Data Source
AI summary
In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.