Semiconductor Test Structure for Metal Wiring Defect Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Defects in semiconductor backend processes, such as impurity introduction and processing errors during metal wiring and via formation, lead to short-circuits, cuts, and incorrect connections, reducing yield and increasing manufacturing costs.

Innovation Solution

A semiconductor device design featuring specific metal patterns and via structures at different levels, allowing for quick and accurate defect detection by electrical testing through pads connected to these patterns, enabling stable electrical connections and identifying defects such as cuts in metal patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional metal wiring and via processes are used, then the semiconductor device can be manufactured with standard processes, but defects such as short-circuits, cuts, and incorrect connections occur, reducing manufacturing yield

Engineering Contradiction:
Improvemanufacturing yieldVSAvoiddefects (short-circuits, cuts, incorrect connections)
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a test structure with metal patterns and via holes at specific locations before final device completion. This preliminary test structure enables early detection of manufacturing defects in metal wiring and via processes, allowing corrective actions to be taken before defective devices are produced at scale, thereby improving manufacturing yield without requiring fundamental changes to the manufacturing process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a test structure as an intermediary element between the manufacturing process and the final device evaluation. This test structure includes metal patterns and via holes that serve as mediators to detect manufacturing defects indirectly, allowing defects to be identified without directly testing every final device, thus improving yield while maintaining standard manufacturing processes

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If comprehensive defect detection methods are implemented, then manufacturing yield can be improved, but testing time and complexity increase

Engineering Contradiction:
Improvedefect detection accuracyVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the defect detection function into a separate, dedicated test structure that is independent of the final device operation. This test structure contains specific metal patterns and via holes that can be tested separately and quickly, allowing comprehensive defect detection without requiring time-consuming testing of the entire device, thus reducing testing time while maintaining detection accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the testing process by creating a dedicated test structure with specific metal patterns and via holes that can be evaluated independently. This segmentation allows defects to be detected in isolated components rather than requiring comprehensive testing of the entire device, significantly reducing testing time while maintaining high detection accuracy for critical manufacturing defects

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8637988B2Semiconductor device and method of testing the same
Publication Date: 2014.01.28 SAMSUNG ELECTRONICS CO LTD
  • US8637988B2 patent drawing
  • US8637988B2 patent drawing
  • US8637988B2 patent drawing

AI summary

There is provided a semiconductor device comprising, a first metal pattern formed at a first metal level and extending in a first direction, a second metal pattern formed at the first metal level, extending in a second direction that is different than the first direction, and disposed on a side of the first metal pattern to be separated from the first metal pattern, a first via structure formed on the first metal pattern, a third metal pattern formed at a second metal level that is different than the first metal level and electrically connected to the first metal pattern by the first via structure, and a first pad electrically connected to the first metal pattern and a second pad electrically connected to the third metal pattern.