Semiconductor Test Structure Generation Using Lithography Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cutting-edge semiconductor manufacturing processes face challenges in reliably printing small features due to process distortions, leading to defects such as open or short circuits, despite adherence to design rules, which can reduce yield and increase costs.
Innovation Solution
A method involving the generation of test layout clips that undergo lithography simulation to identify lithography risk sites, followed by a test chip design with routing structures to test these sites, using algorithms and machine learning to enhance manufacturability risk assessment and electrical testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design rules are followed to ensure manufacturability, then manufacturing constraints are satisfied, but process distortions still cause defects leading to yield reduction
Solution Approach 1:
The patent performs lithography simulation and identifies at-risk patterns before actual manufacturing. By pre-generating test clips with known risk sites and creating routing paths in advance, the system enables early detection of potential defects, allowing design corrections before production and thus improving yield without compromising manufacturability
Solution Approach 2:
The system establishes a feedback loop where lithography simulation results feed into test chip design, which then provides empirical data back to refine design rules and manufacturing processes. This continuous improvement cycle addresses the contradiction by using simulation feedback to predict and prevent yield-reducing defects while maintaining design rule compliance
2Measurement precision
If comprehensive testing of all patterns is performed, then defect detection capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of uniformly testing all patterns, the patent applies local quality by identifying and focusing testing resources on specific at-risk patterns determined through lithography simulation. The system generates test clips selectively based on simulated risk sites, concentrating measurement precision where defects are most likely to occur while avoiding unnecessary testing of low-risk areas, thus reducing overall testing complexity
Solution Approach 2:
The system creates simplified test chip copies that replicate only the critical at-risk patterns identified through simulation, rather than copying entire complex circuits. These test clips serve as representative models that capture essential manufacturing risks, enabling effective defect detection with reduced testing complexity and lower costs
3Productivity
If feature size is reduced to increase device density, then productivity is improved, but process distortion effects increase leading to more defects
Solution Approach 1:
The patent performs lithography simulation at the reduced feature size scale before manufacturing to identify patterns that are particularly susceptible to process distortions. By pre-generating test clips with at-risk sites for the specific reduced feature dimensions, the system enables early detection and correction of printing accuracy issues, allowing high device density to be achieved while maintaining manufacturing precision through targeted validation
Solution Approach 2:
The system dynamically adjusts testing parameters and test clip generation based on the specific feature size being manufactured. By changing the parameters of lithography simulation and test clip generation to match the reduced feature size conditions, the system optimizes defect detection for the specific manufacturing context, thereby maintaining manufacturing precision while enabling higher device density
Data Source
AI summary
A method comprising accessing, by at least one computing system, a plurality of layout blocks comprising a plurality of design patterns for an interconnect layer and identifications of lithography risk sites of the plurality of design patterns, the lithography risk sites corresponding to violations of constraint based checks for simulated physical patterns corresponding to the plurality of design patterns; and generating, by the at least one computing system, a layout comprising the plurality of layout blocks and at least one routing path that is coupled to a subset of the plurality of design patterns having lithography risk sites.