Semiconductor Test System Parallel Frequency Generation

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Solution Overview

Problem

Conventional semiconductor device test systems are inefficient in testing multi-port devices with function blocks operating at different speeds, as they require multiple test operations and often fail to perform reliable tests due to the inability to apply and receive data at varying frequencies simultaneously.

Innovation Solution

A semiconductor device test system that generates multiple signals at different frequencies corresponding to each function block's operating speed, allowing for simultaneous input and output of test data across multiple ports, using a frequency generation unit, block test units, output drivers, and input drivers to determine the functionality of each block.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional single-frequency test system is used to test multi-port semiconductor devices with different operating speeds, then the device complexity is reduced and the system is easier to operate, but the testing time increases and productivity decreases because multiple sequential test operations are required

Engineering Contradiction:
Improvetesting speedVSAvoidtest system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The test system is segmented into multiple independent test channels, each capable of operating at different frequencies. Each channel includes its own frequency generation unit, pattern data generator, and data determination unit, allowing parallel testing of function blocks with different operating speeds simultaneously

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The test system is designed with multi-functional capability to handle different operating frequencies through a single integrated platform. The frequency generation unit can generate multiple frequencies, and the system can adaptively configure test channels to match the specific operating requirements of each function block being tested

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of time

If multiple sequential test operations are performed on function blocks with different operating speeds, then the test system structure is simpler, but the loss of time increases significantly

Engineering Contradiction:
Improvetesting timeVSAvoidtest system structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The test system enables continuous parallel testing operations across multiple function blocks simultaneously. By generating multiple frequencies at the same time and conducting tests in parallel rather than sequentially, the system eliminates idle time and maintains continuous productive action throughout the testing process

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If test data is applied at a frequency higher or lower than the predetermined frequency, then the testing process is faster or more flexible, but the reliability of the test result is degraded

Engineering Contradiction:
Improvetest result reliabilityVSAvoidfrequency adaptation capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

Each test channel is configured with local frequency generation capability tailored to the specific operating frequency requirements of the corresponding function block. This allows each channel to operate at its optimal frequency for reliable testing while maintaining overall system flexibility through independent frequency configuration

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7711512B2System and method for testing semiconductor device
Publication Date: 2010.05.04 SAMSUNG ELECTRONICS CO LTD
  • US7711512B2 patent drawing
  • US7711512B2 patent drawing
  • US7711512B2 patent drawing

AI summary

According to an example embodiment, a semiconductor device test system includes a semiconductor device and a test apparatus. The semiconductor device includes a plurality of function blocks for performing predetermined functions at different operating speeds and a plurality of ports, each corresponding to a respective function block. The test apparatus is adapted to generate a plurality of signals with different frequencies corresponding to each of the operating speeds of the function blocks, to output a plurality of input test data to the ports in response to the signals, and to receive a plurality of output test data from the ports to determine if the semiconductor device is normal.