Semiconductor Device Testing via Standalone Transistor Evaluation
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Solution Overview
Problem
Conventional semiconductor device failure detection methods require the completion of all wiring layers, leading to significant time and cost losses, and are limited by circuit configuration, making it difficult to test transistors independently.
Innovation Solution
A method involving the formation of lower-layer wirings and contact pads on a substrate, followed by a first feed layer to create a test pattern connecting transistor terminals to separate contact pads, allowing for standalone testing before all wiring layers are formed, and subsequent integration into a circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If testing is performed after completion of all wiring layers, then complete device functionality can be evaluated, but significant time and manufacturing cost are lost
Solution Approach 1:
The patent performs preliminary testing of transistors and circuit elements before completing all wiring layers. Test patterns are formed in early stages to evaluate individual components, allowing failure detection before full device assembly, thus reducing time and cost losses while maintaining reliability through staged verification
Solution Approach 2:
The testing process is segmented into multiple stages: individual transistor testing, circuit element testing, and final integrated device testing. This segmentation allows early evaluation of components independently, enabling time savings without compromising overall device functionality assessment
2Reliability
If testing is performed after completion of all wiring layers, then complete circuit functionality can be tested, but manufacturing cost increases significantly
Solution Approach 1:
The patent performs preliminary testing of transistors and circuit elements before completing all wiring layers. Test patterns are formed in early stages to evaluate individual components, allowing failure detection before full device assembly, thus reducing time and cost losses while maintaining reliability through staged verification
Solution Approach 2:
The testing process is segmented into multiple stages: individual transistor testing, circuit element testing, and final integrated device testing. This segmentation allows early evaluation of components independently, enabling cost reduction by identifying failures before expensive subsequent processing steps
3Reliability
If conventional testing methods are used, then complete device testing is possible, but independent transistor testing cannot be performed
Solution Approach 1:
The patent segments the device into independently testable units by forming test patterns that connect to individual transistor terminals through separate contact pads. This allows each transistor to be tested independently while still enabling complete device testing when all components are evaluated
Solution Approach 2:
The patent introduces separate contact pads as intermediary elements that enable independent access to transistor terminals. These contact pads serve as mediators between the test probe and transistor terminals, allowing standalone transistor testing without requiring complete device assembly or relying on circuit configuration
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.