Semiconductor Test Tray Multi-Lot Segmentation

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Solution Overview

Problem

Current semiconductor device test systems cannot simultaneously test semiconductor devices from different lots using the same test program, as the testing of subsequent lots must wait for the completion of previous lots, leading to inefficiencies in productivity.

Innovation Solution

A test method and system that allows loading semiconductor devices from multiple lots onto a test tray, performing a unified test program, and sorting them based on ID and lot information, enabling concurrent testing and reducing waiting times by using a tester handler with automated temperature control and sorting capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If semiconductor devices of different lots are tested sequentially with the same test program, then testing accuracy is maintained, but productivity decreases due to waiting time between lots

Engineering Contradiction:
Improvetesting accuracyVSAvoidproductivity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The test tray is divided into multiple lot regions, with each region dedicated to a specific lot of semiconductor devices. This segmentation allows different lots to be loaded simultaneously onto the same test tray and tested concurrently, eliminating the sequential waiting time while maintaining lot-specific testing accuracy through dedicated region management.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple lots are loaded simultaneously onto the test tray, then productivity increases, but device complexity increases due to lot management requirements

Engineering Contradiction:
ImproveproductivityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A lot management system acts as an intermediary between the test tray and the testing process. This system automatically tracks and manages multiple lots, their respective regions, and test parameters, thereby handling the complexity of simultaneous multi-lot testing without increasing operational burden on users.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The test tray is designed with universal multi-functional capabilities to accommodate multiple lots simultaneously. By incorporating multiple lot regions with standardized interfaces and automated management, the test tray can handle various lot configurations and test programs in a unified manner, reducing the need for separate testing setups.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If sequential testing is performed, then device complexity is minimized, but loss of time increases due to waiting periods

Engineering Contradiction:
Improvedevice complexityVSAvoidwaiting time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The test system enables continuous useful action by allowing multiple lots to be tested simultaneously without interruption. While one lot is being tested in a specific region, another lot can be prepared or tested in a different region, ensuring that the testing process continues without idle waiting periods and maximizing resource utilization.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables simultaneous testing of semiconductor devices from different lots, reducing the time required for loading and unloading and increasing productivity by allowing multiple lots to be tested concurrently without waiting for previous lots to complete their tests.

Implementation Method 1

Temperature information of the memory devices is detected from temperature sensors of the memory devices

Methodology Applied
Scientific EffectTemperature detection:

Implementation Method 2

A temperature of the test chamber is adjusted to compensate for a temperature difference between the detected temperature of the memory devices and a target temperature

Methodology Applied
Scientific EffectTemperature control:

Data Source

PatentUS11112451B2Test method for semiconductor devices and a test system for semiconductor devices
Publication Date: 2021.09.07 SAMSUNG ELECTRONICS CO LTD
  • US11112451B2 patent drawing
  • US11112451B2 patent drawing
  • US11112451B2 patent drawing

AI summary

A test method for a semiconductor device includes: loading a test tray having semiconductor devices of first and second lots arranged thereon into a test chamber; storing lot information of each of the semiconductor devices; performing a test program on each of the semiconductor devices; obtaining ID information of each of the semiconductor devices; matching the ID information with the lot information to generate lot sorting information; and sorting the semiconductor devices based on results of the test program and the lot sorting information.