Semiconductor Testing Interface Control Bit Segmentation
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Solution Overview
Problem
Current periodic random binary sequences (PRBS) testing methods are not compatible with semiconductor device interfaces that utilize control bits, unable to communicate and toggle control bits with testing data, and require chip-level communication pins, which are often unavailable, slowing down the testing process and limiting pre-integration testing capabilities.
Innovation Solution
A testing interface and circuitry system that communicates control and configuration data to sequence generation and checker circuitry within semiconductor devices, allowing for the generation and transmission of test sequences and comparison sequences to detect errors before integration, even with limited pins available, using sequence generation circuitry and sequence checker circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If current PRBS testing methods are used, then testing can be performed, but the testing cannot be completed before stackup integration and control bits cannot be toggled
Solution Approach 1:
The patent segments the test data into separate data bits and control bits, allowing independent handling and toggling of control bits during PRBS testing. This segmentation enables the testing interface to manipulate control bits separately from the main test data stream, resolving the incompatibility issue while maintaining testing efficiency
Solution Approach 2:
The patent introduces a testing interface as an intermediary component that mediates between the PRBS test sequence and the device under test. This interface captures, holds, and toggles control bits in response to data bits, enabling compatibility with control-bit interfaces without modifying the core PRBS testing methodology
2Productivity
If chip-level communication pins are used for test data communication, then testing can proceed, but pins are often unavailable and testing is slowed
Solution Approach 1:
The patent makes existing device pins multi-functional by enabling them to carry both data bits and control bits simultaneously through the testing interface. This eliminates the need for dedicated communication pins while maintaining full testing capability, as the same physical pins serve multiple purposes during the testing process
Solution Approach 2:
The patent merges the data communication function and control signal function into a single communication channel. By combining these functions, the system reduces the number of required physical pins while maintaining the ability to transmit both test data and control information efficiently
Data Source
AI summary
A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.