Semiconductor Testing Structures Planarization Dummy Wafer Bonding
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Solution Overview
Problem
Existing semiconductor testing structures have surface roughness issues due to differing polishing rates of dielectric and conductive layers, leading to protrusions that damage scanning probes and make it difficult to achieve a smooth surface necessary for contact mode scanning capacitance microscopy (SCM) testing.
Innovation Solution
A method involving planarization and removal of conductive structures and insulation layers to expose a smooth surface, followed by bonding with a dummy wafer and subsequent substrate removal to create an even and smooth testing surface, allowing for accurate SCM testing without probe damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If contact mode SCM testing is performed on existing semiconductor device structures, then doping profile measurement is enabled, but the surface roughness prevents accurate measurement and damages the probe
Solution Approach 1:
The device structure is segmented into multiple layers: the original substrate with device structures, a first dielectric layer, conductive structures, a second dielectric layer, and a cap substrate. This segmentation allows independent optimization of each layer, particularly enabling the cap substrate to provide a smooth testing surface while the original substrate maintains device functionality.
Solution Approach 2:
A cap substrate is introduced as an intermediary element that bonds to the top surface of the device structure. This cap substrate provides the smooth, flat surface required for contact mode SCM testing, mediating between the rough device structure surface and the probe requirements.
2Reliability
If conductive structures are retained on the device structure, then electrical functionality is maintained, but surface protrusions prevent smooth SCM testing
Solution Approach 1:
The conductive structures are nested within the dielectric layers, with the first dielectric layer covering the conductive structures and the second dielectric layer covering the first dielectric layer. This nesting arrangement embeds the protruding conductive structures within the layered structure, providing a flat top surface for testing while maintaining the conductive structures' electrical functionality.
3Ease of operation
If the substrate is removed to access the device structure surface, then testing accessibility is improved, but the surface remains too rough for contact mode SCM
Solution Approach 1:
Instead of attempting to smooth the bottom surface of the device structure after substrate removal, the approach is inverted: a cap substrate is bonded to the top surface of the device structure. This provides the smooth testing surface from the opposite direction, allowing contact mode SCM testing to be performed on the cap substrate's smooth surface that interfaces with the device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures a smooth and even testing surface, preventing probe damage and ensuring accurate SCM testing results by maintaining the completeness of the to-be-tested device structure.
Implementation Method 1
bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer
Data Source
AI summary
A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.