Semiconductor Device Testing Power Pin Optimization
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Solution Overview
Problem
The existing methods for testing semiconductor devices often result in overkill or underkill phenomena due to incorrect determination of electrical power supply during the test, leading to erroneous classification of functioning and defective devices.
Innovation Solution
A method involving the application of a reference test pattern to determine the minimum number of power pins required for normal operation, followed by a delay test pattern with increased cycle to prevent overkill and ensure accurate testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the operating speed of the test pattern is reduced to lower transition of signals, then the number of switching operations of a circuit in the scan cell per unit time is reduced and the supplied electric current is reduced, but the operating speed of the test pattern may not sufficiently cover the operating speed in a normal use environment
Solution Approach 1:
The patent applies preliminary action by performing a reference test before the actual test to determine the optimal number of power pins. This preliminary step establishes the test conditions (number of power pins and clock cycle) that will be used in the subsequent actual test, allowing the system to avoid ground bouncing issues without requiring a globally reduced test speed.
Solution Approach 2:
The patent changes parameters dynamically based on test results. The number of power pins is adjusted according to the reference test outcomes, and the clock cycle of the test pattern is modified to match the determined optimal number of power pins. This parameter adaptation allows the system to achieve low current consumption while maintaining sufficient operating speed coverage.
2Speed
If the number of switching operations of a circuit in the scan cell is increased to cover normal operation speed, then the supplied electric current is increased, but ground bouncing is generated and overkill occurs
Solution Approach 1:
The reference test serves as a preliminary action that identifies the optimal test conditions before the actual test. By determining the appropriate number of power pins and clock cycle in advance, the system can proceed with high-speed testing without encountering ground bouncing issues that would cause overkill.
Solution Approach 2:
The patent implements feedback by using the results of the reference test to adjust the test conditions for the actual test. The number of power pins and clock cycle are modified based on feedback from the reference test, creating a closed-loop system that adapts to prevent ground bouncing while maintaining high operating speed.
3Loss of energy
If power pins are removed during normal operation to reduce current, then ground bouncing is reduced, but the test condition becomes suboptimal for accurate testing
Solution Approach 1:
The reference test is performed as a preliminary action to determine the optimal number of power pins before the actual test. This ensures that when power pins are removed during the actual test, the remaining configuration is optimized for both low current consumption and high test accuracy, avoiding suboptimal test conditions.
Solution Approach 2:
The system changes the number of power pins parameter based on reference test results, but also adjusts the clock cycle parameter to compensate. This dual parameter adjustment ensures that even with fewer power pins, the test maintains sufficient speed and accuracy by optimizing the timing characteristics.
Data Source
AI summary
A method of testing a semiconductor device including applying a reference test pattern to the semiconductor device in which a preset number of power pins of the semiconductor device are supplied with current, incrementally disconnecting the power pins from the current to set a number of removal power pins, and determining a final number of power pins which represents a minimum number of power pins with which the semiconductor device operates normally. The method additionally includes applying a delay test pattern to the semiconductor device to set a cycle of the delay test pattern corresponding to the number of removal power pins to reduce or prevent an overkill phenomenon.