Semiconductor Testline Structure for Backside Probe Pad Integration
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Solution Overview
Problem
Conventional testline structures in semiconductor integrated circuits are inadequate for advanced semiconductor devices due to the introduction of backside power rails, which require improved backside testing structures and increased housing of DUTs on a shrunk testline area.
Innovation Solution
The implementation of backside probe pads and a probe pad structure that includes both frontside and backside portions, allowing for backside probing and accommodating more DUTs on a reduced testline area, with the structure comprising frontside and backside interconnects connected via contact vias and doped epitaxial features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If backside power rails are introduced to reduce resistance and voltage drop, then power delivery efficiency is improved, but testline structure complexity increases and existing testline structures become inadequate
Solution Approach 1:
The patent introduces backside power rails by utilizing the backside dimension of the semiconductor device, moving power delivery from a single-sided (frontside) approach to a multi-dimensional approach. This allows power rails to be formed on both the frontside and backside of the device, reducing resistance without significantly increasing testline complexity on the frontside.
Solution Approach 2:
The testline structure is segmented into frontside and backside portions, with probe pads and interconnects distributed across both surfaces. This segmentation allows testing functionality to be maintained on the frontside while power delivery is enhanced through backside rails, resolving the conflict between power efficiency and testline simplicity.
2Area of stationary object
If testline area is reduced to accommodate scaling, then chip area efficiency is improved, but the number of DUTs that can be housed decreases
Solution Approach 1:
The patent extends the testline structure into the backside dimension, allowing DUTs to be housed on both frontside and backside surfaces. This vertical expansion into another dimension effectively doubles the available testline area without increasing the planar footprint, maintaining area efficiency while increasing DUT capacity.
Solution Approach 2:
The backside probe pads and interconnects are nested within the overall testline structure, utilizing the backside surface as an additional layer of functionality. This nesting approach allows more DUTs to be accommodated within the same device footprint by efficiently packing testing resources across multiple surfaces.
3Adaptability or versatility
If more probe pads are added to accommodate backside probing and increased DUT housing, then testing capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of backside power rails with the formation of backside probe pads and interconnects, using shared process steps such as dielectric deposition, patterning, and etching. This consolidation of manufacturing steps increases testing capability while minimizing the increase in manufacturing complexity by reusing existing process infrastructure.
Data Source
AI summary
A semiconductor device includes a circuit region, a seal ring region encircling the circuit region, and a testline region aside the seal ring region. The circuit region includes first transistors disposed over a substrate, a first frontside interconnect structure disposed over the substrate and electrically coupled to the first transistors, and a first backside interconnect structure disposed under the substrate and electrically coupled to the first transistors. The seal ring region includes a second frontside interconnect structure disposed over the substrate. The testline region includes second transistors disposed over the substrate, the second transistors including epitaxial features, a third frontside interconnect structure disposed over the epitaxial features, and a second backside interconnect structure disposed under the epitaxial features. The third frontside interconnect structure includes a frontside probe pad. The second backside interconnect structure includes a backside probe pad.