Semiconductor Light Emitting Device Textured Surface Contact
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Solution Overview
Problem
Existing semiconductor light-emitting devices face challenges in substrate removal without damaging the material due to aggressive bonding conditions caused by topography variations, which can lead to material damage during flip-chip bonding.
Innovation Solution
A compliant bonding structure is implemented using a thick metal n-contact with micron-scale semiconductor islands or bumps, allowing for a robust, mechanical, thermal, and electrical connection that compensates for height differences between n-type and p-type regions, reducing the need for aggressive bonding conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard flip-chip bonding process is used on textured surfaces, then bonding can proceed, but material damage occurs due to aggressive bonding conditions caused by topography variations
Solution Approach 1:
The contact structure is segmented into multiple components: a textured surface region, a planarized dielectric layer, and a metal contact layer. This segmentation allows the textured surface to maintain its light-diffusing function while the overlying planar layers provide a flat bonding surface, eliminating the harmful effect of topography variations during bonding.
Solution Approach 2:
A planarizing dielectric layer is introduced as an intermediary between the textured semiconductor surface and the bonding interface. This intermediate layer absorbs the topography variations and provides a flat surface for bonding, preventing material damage while maintaining bonding reliability.
2Reliability
If the n-type region is etched through the p-type region to form openings, then electrical contact to the n-type region is achieved, but height differences create topography variations that cause bonding problems
Solution Approach 1:
The contact structure is segmented into multiple components: a textured surface region, a planarized dielectric layer, and a metal contact layer. This segmentation allows the textured surface to maintain its light-diffusing function while the overlying planar layers provide a flat bonding surface, eliminating the harmful effect of topography variations during bonding.
Solution Approach 2:
The solution addresses the surface topography problem by moving to another dimension - adding vertical layers (dielectric and metal) over the textured surface. This creates a planar bonding interface at a higher elevation, effectively decoupling the electrical contact function from the bonding surface topology.
3Object-affected harmful factors
If thick contacts are used to compensate for height differences, then bonding can proceed without damage, but device complexity and material usage increase
Solution Approach 1:
The contact structure is segmented into multiple components: a textured surface region, a planarized dielectric layer, and a metal contact layer. This segmentation allows the textured surface to maintain its light-diffusing function while the overlying planar layers provide a flat bonding surface, eliminating the harmful effect of topography variations during bonding.
Solution Approach 2:
A planarizing dielectric layer is introduced as an intermediary between the textured semiconductor surface and the bonding interface. This intermediate layer absorbs the topography variations and provides a flat surface for bonding, preventing material damage while maintaining bonding reliability.
Data Source
AI summary
A device includes a semiconductor structure comprising a light emitting layer (24) disposed between an n-type region (22) and a p-type region (26). The semiconductor structure includes an n-contact region (23) and a p-contact region (25). A cross section of the n-contact region (23) comprises a plurality of first regions (28) wherein portions of the light emitting layer (24) and p-type region (26) are removed to expose the n-type region (22). The plurality of first regions (28) are separated by a plurality of second regions (27) wherein the light emitting layer (24) and p-type region (26) remain in the device. The device further includes a first metal contact (40) formed over the semiconductor structure in the p-contact region (25) and a second metal contact (38) formed over the semiconductor structure in the n-contact region (23). The second metal contact (38) is in electrical contact with at least one of the second regions (27) in the n-contact region (23).


