Semiconductor Device Thermal Oxide Region for RESURF Performance
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Solution Overview
Problem
Lateral RESURF devices face challenges in achieving reproducible high breakdown voltage and low on-state resistance due to sensitivity to charge balance and current pinching issues, limiting their performance and manufacturability.
Innovation Solution
A method involving a two-stage thick oxide process with in-trench oxidation and nitride spacer etching to create a thermal oxide region, allowing for increased epi silicon doping and reduced cell pitch without compromising breakdown voltage, resulting in lower on-state resistance and improved charge handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If deep p-type super junction pillars are used to achieve RESURF, then breakdown voltage is improved, but current flow is restricted between pillars
Solution Approach 1:
The patent removes the deep p-type super junction pillars from the structure, extracting the harmful current pinching effect while preserving the beneficial RESURF breakdown voltage characteristics through alternative means (trench isolation with oxide filling)
Solution Approach 2:
The patent applies localized oxide filling only in the trench regions between cells, creating local isolation structures that prevent current pinching without affecting the overall epi layer doping profile and charge balance across the device
2Productivity
If cell pitch is reduced to increase cell density, then device integration is improved, but current pinching between super junction pillars worsens
Solution Approach 1:
By removing the deep p-type pillars that cause current pinching, the patent enables reduced cell pitch designs where adjacent cells can be placed closer together without harmful current restriction effects
Solution Approach 2:
The patent performs preliminary trench isolation and oxide filling during the fabrication process, preparing the structure in advance to prevent current pinching before cells are placed at reduced pitch, thereby enabling higher cell density
3Reliability
If epi silicon doping is increased to reduce on-state resistance, then conductivity is improved, but breakdown voltage control becomes more difficult
Solution Approach 1:
The patent applies localized oxide filling in trench regions that creates electric field termination and charge compensation effects, allowing higher overall epi doping for lower on-state resistance while maintaining precise breakdown voltage control through the localized charge distribution in the oxide-filled trenches
Solution Approach 2:
The patent changes the physical and chemical parameters of the isolation structures by using oxide filling with specific dielectric properties, which alters the electric field distribution and charge balance, enabling simultaneous optimization of on-state resistance and breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach achieves a 35% improvement in specific on-state resistance and comparable dynamic charge handling, enabling better RESURF performance without the need for narrow cell pitches or high gate charge structures.
Implementation Method 1
perform a thermal oxidation, wherein a thermal oxide region is created, since the oxide is extended at the position of the first lateral part of the nitride
Implementation Method 2
since the nitride bends upwards
Data Source
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AI summary
This disclosure relates to a semiconductor device, which semiconductor device comprises a gate electrode, the gate electrode comprising an upper side and a bottom side, a dielectric oxide on the upper side of the gate electrode and a deposited oxide on the bottom side of the gate electrode, wherein the deposited oxide has a first width. Between the deposited oxide and the gate electrode a thermal oxide region is located, wherein the thermal oxide region has a second width, wherein the second width of the thermal oxide region is broader than the first width of the deposited oxide.