Semiconductor Device Thermal Stress Dispersion via Inorganic Insulation Film
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Solution Overview
Problem
Semiconductor devices face thermal stress issues during mounting due to differences in the coefficient of linear expansion between semiconductor portions and metal wiring, leading to potential damage from thermal stress propagation from the mounting board, sealing resin, and bump materials.
Innovation Solution
A semiconductor device design incorporating an inorganic insulation film and an organic insulation film, where the inorganic insulation film is more resistant to deformation, disperses thermal stress through contact with the second wiring, reducing concentration on unit transistors and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wiring is used to connect the semiconductor portion, then electrical connectivity is achieved, but thermal stress occurs due to difference in coefficient of linear expansion between the semiconductor portion and metal wiring
Solution Approach 1:
An inorganic insulation film is introduced as an intermediary layer between the metal wiring and the semiconductor portion. This film has a coefficient of linear expansion that matches the semiconductor substrate, thereby reducing thermal stress during heating treatment while maintaining electrical connectivity through openings in the film.
Solution Approach 2:
The coefficient of linear expansion parameter is matched between the inorganic insulation film and the semiconductor substrate. By selecting an inorganic material with appropriate thermal expansion characteristics, the patent reduces the differential thermal stress that would otherwise occur between dissimilar materials during temperature changes.
2Reliability
If insulation films are used between wiring layers, then electrical insulation is achieved, but parasitic capacitance is generated between the wiring
Solution Approach 1:
The inorganic insulation film is selectively positioned only where needed for stress reduction, rather than forming a continuous layer. Openings are provided in the film to allow wiring to pass through, thereby maintaining electrical insulation where required while minimizing parasitic capacitance by reducing the overall area of the insulation film between conductive layers.
3Ease of manufacture
If the semiconductor device undergoes heating treatment during mounting, then the device is secured to the mounting board, but thermal stress propagates from the mounting board, sealing resin, and bump materials to the semiconductor portion
Solution Approach 1:
The inorganic insulation film acts as a stress buffer between the mounting board assembly (including sealing resin and bump materials) and the sensitive semiconductor portion. During heating treatment, this film absorbs and distributes thermal stress, preventing stress concentration and propagation to the HBT and other semiconductor components.
4Device complexity
If a single layer of insulation film is used, then the structure is simple, but it cannot effectively disperse thermal stress while maintaining low parasitic capacitance
Solution Approach 1:
The patent employs a composite insulation structure combining organic insulation material and inorganic insulation film. The organic material provides baseline insulation with low parasitic capacitance, while the inorganic film layer specifically addresses thermal stress dispersion. This composite approach achieves both thermal and electrical performance requirements without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces thermal stress on unit transistors, suppressing deformation and damage, while also reducing parasitic capacitance and enhancing moisture resistance and heat dissipation performance.
Implementation Method 1
thermal stress due to a difference in coefficient of linear expansion between the semiconductor portion and metal wiring of the semiconductor device occurs near an interface where the semiconductor portion and the metal wiring are in contact
Implementation Method 2
Since the inorganic insulation film is deformed less easily than the organic insulation film, deformation of the second wiring due to thermal stress can be suppressed
Implementation Method 3
enhancing moisture resistance and heat dissipation performance
Data Source
AI summary
At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.