Semiconductor Device Third Region Avalanche Control

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Solution Overview

Problem

Conventional semiconductor devices face challenges in suppressing avalanche and maintaining the reliability of the gate insulating film under high voltage conditions, leading to potential dielectric breakdown and reduced reliability.

Innovation Solution

The semiconductor device incorporates a p-type third semiconductor region with a higher impurity concentration and deeper depth than the p-type first semiconductor region, strategically positioned beneath the gate pad or in the active region, to induce avalanche and thereby suppress the application of high electric fields to the gate insulating film, enhancing its resistance to breakdown.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional semiconductor device structure is used, then the device can operate, but avalanche occurs in the vicinity of the gate insulating film under high voltage conditions, leading to dielectric breakdown and reduced reliability

Engineering Contradiction:
Improvegate insulating film reliabilityVSAvoidavalanche and high electric field stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A third semiconductor region of the second conductivity type is introduced as an intermediary structure between the drain electrode and the gate insulating film. This third region has an impurity concentration higher than the first semiconductor region and is positioned deeper in the drift region, serving to intercept and manage avalanche activity away from the gate insulating film, thereby protecting it from high electric field stress and dielectric breakdown

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies local quality by creating a non-uniform impurity concentration distribution in the drift region. The third semiconductor region has a locally higher impurity concentration compared to the first semiconductor region, and this localized modification is strategically positioned to control avalanche behavior specifically in the vicinity of the gate insulating film without affecting other regions of the device

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively prevents avalanche in the vicinity of the gate insulating film, improving its resistance to breakdown and overall reliability by ensuring the gate insulating film is not subjected to excessive electric stress.

Implementation Method 1

the third semiconductor region... to induce avalanche and thereby suppress the application of high electric fields to the gate insulating film

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS10644145B2Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2020.05.05 FUJI ELECTRIC CO LTD
  • US10644145B2 patent drawing
  • US10644145B2 patent drawing
  • US10644145B2 patent drawing

AI summary

A semiconductor device, including a semiconductor substrate, a semiconductor layer disposed on a surface of the semiconductor substrate, a first semiconductor region disposed in the semiconductor layer at a surface thereof, a source region and a second semiconductor region disposed in the first semiconductor region at a surface thereof, a source electrode contacting the source region and the second semiconductor region, a gate insulating film disposed on the surface of the semiconductor layer and covering a portion of the first semiconductor region between the source region and the semiconductor layer, a gate electrode disposed on a surface of the gate insulating film, a drain electrode disposed on another surface of the semiconductor substrate, and a third semiconductor region, which has an impurity concentration higher than that of the first semiconductor region, formed in the semiconductor layer at the surface thereof and being electrically connected to the source electrode.