Semiconductor Through-Hole Electrode via Single-Step Etching

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Solution Overview

Problem

The existing method for manufacturing semiconductor devices with through-hole electrodes is inefficient due to the need for multiple photolithographic steps and separate etching processes, leading to increased manufacturing time and cost, as well as variations in interlayer insulating film thickness causing issues with contact hole formation and metal layer damage.

Innovation Solution

A method involving the formation of conductive polysilicon contact pads that allow for the creation of via holes in a single step, eliminating the need for separate etching of the semiconductor silicon layer and interlayer insulating film, and using anisotropic etching with a metal contact pad as an etching stopper to prevent faulty etching or over-etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate etching processes are used for semiconductor silicon layer and interlayer insulating film, then etching precision can be controlled, but manufacturing time and process complexity increase

Engineering Contradiction:
Improveetching precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines the etching of the semiconductor silicon layer and the interlayer insulating film into a single continuous etching process. The via hole is formed by etching through both layers sequentially without breaking the process, eliminating the need for separate etching steps while maintaining precision through controlled etching parameters and intermediate protective layers.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies a protective film on the rear surface of the semiconductor silicon layer before the etching process begins. This preliminary protective layer prevents damage to the rear surface during etching and allows the etching process to proceed through the front surface without requiring separate handling steps, thereby reducing manufacturing time while preserving precision.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple photolithographic steps are used, then via hole formation precision is improved, but process complexity and manufacturing cost increase

Engineering Contradiction:
Improvevia hole formation precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple photolithographic steps into a single photolithography process. By designing the photoresist pattern and etching process to achieve both semiconductor layer penetration and insulating film removal in one step, the number of photolithography applications is reduced while maintaining via hole formation precision through optimized etching control.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If interlayer insulating film thickness is reduced, then contact hole formation becomes easier, but film thickness variation causes metal layer damage

Engineering Contradiction:
Improvecontact hole formation easeVSAvoidmetal layer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies a protective film on the rear surface of the semiconductor silicon layer before etching. This preliminary protective layer acts as a buffer that prevents over-etching from damaging the metal layers, allowing the use of thinner interlayer insulating films without compromising metal layer integrity. The protective film ensures that even with thickness variations, the etching process stops at the correct depth.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If single-step via hole formation is used, then manufacturing time is reduced, but precision in forming through-hole electrodes may deteriorate

Engineering Contradiction:
Improvemanufacturing speedVSAvoidthrough-hole electrode precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent combines the formation of the via hole through the semiconductor layer and the removal of the interlayer insulating film into a single continuous etching process. This merging maintains precision by using controlled etching parameters, intermediate protective layers, and a single photolithography step with optimized patterning to ensure accurate via hole formation while improving productivity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The protective film applied on the rear surface before etching serves as a preliminary measure that enables single-step via hole formation with high precision. It prevents damage during the etching process and allows the etching to proceed through both layers in one step without compromising the final electrode precision, thereby achieving both speed and accuracy.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process, improves precision in forming through-hole electrodes, reduces manufacturing time and cost, and enhances the yield of semiconductor devices by eliminating the need for additional steps and minimizing variations in film thickness.

Implementation Method 1

using anisotropic etching with a metal contact pad as an etching stopper to prevent faulty etching or over-etching

Methodology Applied
Scientific EffectAnisotropic etching:

Data Source

PatentUS8004090B2Semiconductor device and method for manufacturing the same
Publication Date: 2011.08.23 LONGITUDE LICENSING LTD
  • US8004090B2 patent drawing
  • US8004090B2 patent drawing
  • US8004090B2 patent drawing

AI summary

A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the semiconductor silicon layer and the first contact pad and reaches to the second contact pad.