3D Semiconductor Through-Hole Geometry for Uniform Sacrificial Etching
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Solution Overview
Problem
Current 3D stacked semiconductor structures exhibit poor morphology due to high aspect ratios in through-holes, leading to uneven etching of sacrificial layers, which affects the performance of memory devices by exposing large top surfaces and small bottom surfaces of semiconductor columns.
Innovation Solution
A method is developed to form through-holes with a wider bottom than top, controlling the etching ratio to ensure balanced exposure of sacrificial layers, thereby maintaining consistent morphology of semiconductor columns and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form through-holes in isolation structures, then the through-holes can be formed, but the aspect ratio becomes too high causing uneven etching of sacrificial layers
Solution Approach 1:
The patent applies asymmetry by designing the through-hole with a trapezoidal cross-section where the bottom width is greater than the top width. This asymmetric geometry compensates for the natural etching tendency that creates larger openings at the top, resulting in more uniform sacrificial layer exposure throughout the through-hole depth.
Solution Approach 2:
The patent changes the geometric parameters of the through-hole by controlling the etching process to create a specific width ratio (0.75-0.95) between top and bottom. This parameter optimization ensures that the etched sacrificial layer maintains consistent thickness, improving manufacturing precision.
2Ease of manufacture
If the through-hole has a standard cylindrical shape, then the fabrication process is simple, but the top surface of sacrificial layer is exposed too much while bottom surface is exposed too little
Solution Approach 1:
The patent transforms the symmetric cylindrical through-hole into an asymmetric trapezoidal through-hole with controlled width variation. This asymmetric shape is specifically designed to compensate for etching effects, ensuring uniform sacrificial layer exposure while maintaining reasonable fabrication complexity through established etching processes.
3Productivity
If the width ratio of through-hole top to bottom is not controlled, then the etching process is simpler, but the morphology of semiconductor columns becomes inconsistent
Solution Approach 1:
The patent optimizes the width ratio parameter of the through-hole to a specific range (0.75-0.95). This parameter control ensures that the etching process maintains consistent morphology of semiconductor columns throughout the structure, improving manufacturing precision while preserving etching process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the etching of sacrificial layers is balanced, resulting in consistent exposure of top and bottom surfaces of semiconductor columns, enhancing the morphology and performance of semiconductor structures.
Implementation Method 1
The etching process is performed on the first sacrificial layer exposed by the through-hole
Data Source
AI summary
A method for fabricating a semiconductor structure and the device are disclosed. The method includes: providing a first sacrificial layer and semiconductor columns on a substrate; forming an isolation structure, disposed between adjacent stacked structures along the first direction; etching the isolation structure to form a through-hole, the through-hole exposes a part of the surface of the substrate, and also exposes each side of each stacked structure; along the second direction, the width of the bottom of the through-hole is greater than the width of the top of the through-hole, and the second direction is perpendicular to the first direction; the first sacrificial layer exposed by the through-hole is laterally etched, and a part of the first sacrificial layer is removed. A sacrificial layer exposes the top surface and the bottom surface of each semiconductor column. The present disclosure improves the morphology of the semiconductor structure.