Semiconductor Through Hole Structure Level Alignment
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Solution Overview
Problem
The complexity of wiring in semiconductor apparatuses with multilayered structures leads to increased thickness of inter-layer insulating layers, which can cause wire breakage and reliability issues due to differences in levels between through hole openings and insulating layer openings.
Innovation Solution
A semiconductor apparatus with a through hole structure where the insulating layer opening is of the same size and position as the through hole opening, and a manufacturing method involving etching the semiconductor substrate from the second principal surface side to form a taper-shaped through hole, using the inter-layer insulating layer as an etch mask to prevent wire breakage and maintain high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the electrode pad is formed of the topmost wiring layer of multilayered wiring, then the wiring complexity is reduced, but the total thickness of inter-layer insulating layers increases causing level differences and wire breakage
Solution Approach 1:
The patent extracts the electrode pad from the multilayered wiring structure and places it on the semiconductor substrate surface, separate from the inter-layer insulating layers. This eliminates the need for the electrode pad to be part of the topmost wiring layer, allowing the wiring structure to maintain its multilayered complexity while the electrode pad sits at a different level, thus resolving the level difference issue between the through hole opening and insulating layer opening.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming the through hole to penetrate through the inter-layer insulating layers and reaching the semiconductor substrate surface where the electrode pad is located. This creates a new vertical pathway that bypasses the horizontal level difference problem, allowing electrical connection without requiring the electrode pad to be at the same level as the insulating layer opening.
2Ease of manufacture
If photoresist is used as etch mask, then the etching process can be performed, but photoresist residues remain causing contamination and requiring additional cleaning steps
Solution Approach 1:
The patent uses a disposable etch mask layer that is specifically designed to be removed after etching. This mask layer performs its function during the etching process and is then completely removed, leaving no residues. The mask is sacrificed for the purpose of enabling the etching process without the long-term contamination issues of photoresist.
Solution Approach 2:
The patent changes the material parameter of the etch mask from photoresist to a different material that does not leave residues. This material parameter change allows the etching process to proceed effectively while eliminating the harmful residue generation, as the new mask material can be completely removed or decomposed after serving its purpose.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces wire breakage and enhances the reliability of semiconductor apparatuses by ensuring no difference in level between the through hole opening and insulating layer opening, while also avoiding the adverse effects of photoresist residues and maintaining high productivity.
Implementation Method 1
the present applicant discloses a semiconductor apparatus having a taper-shaped through hole using an anisotropic etching method
Implementation Method 2
an inter-layer insulating layer etching step of etching the inter-layer insulating layers from the second principal surface side using the semiconductor substrate in which the through hole is formed as an etch mask
Data Source
AI summary
A semiconductor apparatus including a semiconductor substrate having a first principal surface on which an electric circuit is formed and a second principal surface opposed to the first principal surface, and a through hole that penetrates the first principal surface and the second principal surface, a multilayered wiring layer having a plurality of conductive wiring layers connected to the electric circuit and a plurality of inter-layer insulating layers having an insulating layer opening of a same size and at a same position as a through hole opening which is an opening of the first principal surface of the through hole, an electrode pad that covers the insulating layer opening connected to the conductive wiring layer and a lead-out wiring layer having a through wiring layer connected to the electrode pad formed inside the through hole and a connection wiring layer formed integral with the through wiring layer.