Semiconductor Through-Hole Formation via Sacrificial Layer Template
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Solution Overview
Problem
Conventional techniques struggle to form through-holes in semiconductor devices with node sizes below 50 nm, particularly for ETOX-structure non-volatile memory, due to difficulties in achieving a straight shape and avoiding OVL offset, which affects electrical performance.
Innovation Solution
A manufacturing method involving the formation of shallow trench isolations, sacrificial layers, and reverse through-hole processes to create self-aligned, straight through-holes that maintain the shape of the control gate, eliminating OVL offset and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional through-hole processes are used to form through-holes in semiconductor devices with node sizes below 50 nm, then the manufacturing process can be completed, but the through-holes exhibit OVL offset and non-straight shapes that cannot meet electrical requirements
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer between the gates before forming the through-holes. This sacrificial layer serves as a template that defines the precise position and straight shape of the through-holes. The isolation strips are formed on this sacrificial layer, creating a self-aligned structure that eliminates OVL offset. After the through-holes are formed, the sacrificial layer is removed. This preliminary structuring enables high-precision through-hole formation at node sizes below 50 nm.
Solution Approach 2:
The patent uses the sacrificial layer as an intermediary element that facilitates the formation of straight through-holes without OVL offset. The sacrificial layer acts as a mediator between the gate structure and the final through-hole configuration. Additionally, the isolation strips serve as intermediaries that protect the shallow trench isolations during the through-hole formation process and enable precise alignment. These intermediary elements are removed or transformed after serving their purpose, leaving the desired through-hole structure.
2Area of moving object
If the size of drain between floating gates is reduced to meet high-density market demands, then storage density increases, but the through-hole process becomes increasingly difficult with greater OVL and shape challenges
Solution Approach 1:
The patent applies self-service by creating a self-aligned structure where the sacrificial layer and isolation strips automatically define the through-hole positions and shapes. The isolation strips are formed directly on the sacrificial layer in the spaces between shallow trench isolations, creating inherent alignment that eliminates the need for separate alignment processes. This self-aligned approach enables precise through-hole formation even as drain sizes are reduced to increase storage density, making the manufacturing process easier despite smaller dimensions.
Solution Approach 2:
The patent segments the through-hole formation process into distinct stages: first forming the sacrificial layer, then forming isolation strips on specific portions of the sacrificial layer, and finally forming through-holes in the remaining spaces. This segmentation allows each step to be optimized independently and enables precise control over through-hole geometry even at reduced drain sizes, overcoming the difficulties of conventional single-step through-hole processes.
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method therefor. The manufacturing method for a semiconductor device is provided for forming through-holes in a semiconductor device, comprising: forming a plurality of shallow trench isolations in portions of a substrate corresponding to memory cell regions; forming a plurality of gates on surfaces of the portions of the substrate; forming spacers on side walls at both sides of the gates extending in the first direction; depositing a sacrificial layer on the memory cell region; removing portions of the sacrificial layer corresponding to the shallow trench isolations at memory cell drain, and depositing an isolation dielectric on the shallow trench isolations at the memory cell drain to form isolation strips; and removing the remaining sacrificial layer to form bottom through-holes in spaces formed after removing the remaining sacrificial layer.