Semiconductor Through Interconnects via Mating Projections
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Solution Overview
Problem
As semiconductor components become smaller and have higher input/output configurations, there is a need for through interconnects with increasingly smaller sizes and pitches without compromising signal transmission performance and reliability, while also being capable of volume manufacture using existing equipment and techniques.
Innovation Solution
The solution involves the use of through interconnects with substrate openings and projections formed using anisotropic etching processes, where the substrate openings and projections on the semiconductor and interposer substrates have mating sizes and shapes, and are configured for physical and electrical engagement, with conductive vias providing separate electrical paths, and optionally filled with a polymer underfill material for additional bonding and insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through interconnects are made smaller to support higher I/O configurations, then component size and pin count are improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The through interconnect fabrication is segmented into multiple sequential steps: forming substrate openings, forming projections, forming conductive vias, and filling with underfill material. This segmentation allows each step to be optimized independently, maintaining precision even as overall dimensions are reduced.
Solution Approach 2:
Projections are formed on the interposer substrate in advance, before the substrate openings are formed in the semiconductor substrate. This preliminary action ensures that the projections are already in position and can guide the formation of precisely sized openings, maintaining manufacturing precision at smaller scales.
2Volume of moving object
If through interconnects are made with smaller sizes and pitches, then component size is reduced, but signal transmission performance and reliability may be compromised
Solution Approach 1:
The through interconnect is constructed as a composite structure with multiple materials: conductive material for electrical pathways and polymer underfill material for mechanical support and insulation. This composite approach maintains signal transmission reliability by ensuring proper electrical properties even in miniaturized structures.
Solution Approach 2:
The polymer underfill material acts as an intermediary between the conductive vias and the surrounding substrate. It provides mechanical support, thermal management, and electrical insulation, ensuring that the small-scale conductive pathways maintain their integrity and reliability for signal transmission.
3Reliability
If through interconnects are fabricated with precise mating sizes and shapes, then connection reliability is improved, but device complexity increases
Solution Approach 1:
The substrate openings and projections are designed with specific local geometries optimized for their function. The openings have dimensions and shapes tailored to receive the projections with precise fit, while the projections have complementary geometries. This local optimization achieves reliable engagement without requiring complex overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor components with reliable and efficient signal transmission systems, enabling the creation of smaller, more complex semiconductor components while maintaining performance and facilitating volume manufacturing.
Implementation Method 1
substrate openings and projections formed using anisotropic etching processes
Data Source
AI summary
A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately a second semiconductor substrate), forming projections on the interposer substrate (or on the second semiconductor substrate), and forming conductive vias in the projections. The method can also include the steps of placing the projections in physical contact with the openings, and placing the conductive vias in electrical contact with the substrate contacts. The method can also include the steps of bonding the conductive vias to the substrate contacts, and forming terminal contacts on the interposer substrate (or alternately on one of the semiconductor substrates) in electrical communication with the conductive vias.