Semiconductor Device Through-Output Synchronization Bits

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Solution Overview

Problem

In semiconductor devices with serial communication functions, sampling errors accumulate in multi-stage connections, leading to increased risk of overrun errors due to shorter guard bits, which can be mitigated but result in reduced communication speed.

Innovation Solution

The semiconductor device employs a logic circuit to detect synchronization bits and calculate the baud rate, controlling an output stage to through-output synchronization bits without sampling, thereby preventing error accumulation and maintaining guard bit length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sampling is performed at each stage in multi-stage connections, then data transmission can be processed, but sampling errors accumulate leading to overrun errors

Engineering Contradiction:
Improvedata transmission processingVSAvoidsampling error accumulation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the signal processing into two distinct paths: synchronization bits are extracted and handled separately from the message string. The synchronization bit extraction unit isolates synchronization bits before they can cause error accumulation, while the message string processing unit handles data transmission. This segmentation prevents sampling errors from accumulating across multiple stages while maintaining processing productivity.

Inventive Principle:
Principle #1Segmentation

2Speed

If guard bit length is reduced to increase communication speed, then communication efficiency improves, but overrun error risk increases

Engineering Contradiction:
Improvecommunication speedVSAvoidoverrun error risk
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by extracting synchronization bits before the main data processing occurs. The synchronization bit extraction unit prepares and separates synchronization bits in advance, allowing the message string processing to proceed without waiting for synchronization processing. This preliminary separation enables faster communication while maintaining reliable error-free transmission by preventing the interleaving of synchronization and data processing that causes overrun errors.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If synchronization bits are processed through the logic circuit, then proper synchronization is achieved, but sampling errors accumulate

Engineering Contradiction:
Improvesynchronization stabilityVSAvoidsampling error accumulation
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent extracts synchronization bits from the combined signal stream before they can interact with the message string processing. The synchronization bit extraction unit takes out synchronization bits and routes them through a separate path that does not involve the logic circuit sampling operations. This extraction maintains synchronization stability while preventing the sampling errors that would occur if synchronization bits were processed through the same logic circuit as message data.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240364442A1Semiconductor device and electronic appliance
Publication Date: 2024.10.31 ROHM CO LTD
  • US20240364442A1 patent drawing
  • US20240364442A1 patent drawing
  • US20240364442A1 patent drawing

AI summary

A semiconductor device is used as one of a plurality of slaves connected in multiple stages to a master and transmits a frame signal output from the master sequentially from a preceding stage to a subsequent stage. The frame signal includes synchronization bits and a message string (for example, command bits, address bits, and guard bits) following the synchronization bits. The semiconductor device includes a logic circuit configured to sample the frame signal at a baud rate corresponding to the synchronization bits and an output stage configured to through-outputs the synchronization bits before sampling without passing them through the logic circuit.