3D Semiconductor Through-Via Bundles for Capacitance and Noise Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D semiconductor packages face limitations in electrical and mechanical reliability due to the connection structure between semiconductor chips, necessitating improvements in capacitance and resistance adjustments to maintain optimal electrical performance.
Innovation Solution
The semiconductor chip incorporates through via structures of different shapes and configurations, including first and second through via structure bundles, to adjust capacitances and resistances, preventing deterioration of electrical performance by varying their vertical lengths and insulation layer thicknesses, and positioning them in specific keep out zones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through via structures with uniform design are used, then manufacturing is simplified, but electrical performance deteriorates due to inability to adjust capacitance and resistance
Solution Approach 1:
The patent applies local quality by creating different via structure types (first via structures with longer vertical length and thicker insulation layers, second via structures with shorter vertical length and thinner insulation layers) positioned at different locations on the substrate. This allows different regions to have optimized electrical characteristics - the first via structures provide higher capacitance and resistance for noise shielding, while the second via structures provide lower capacitance and resistance for signal transmission, thereby improving overall electrical performance without requiring complete redesign of all via structures.
2Reliability
If via structures extend through the entire substrate thickness, then vertical connectivity is improved, but capacitance and resistance cannot be optimized for different regions
Solution Approach 1:
The patent segments the via structures into two distinct types based on their vertical extent and insulation layer thickness. First via structures extend through the entire substrate thickness with thicker insulation layers to provide high capacitance and resistance for noise shielding. Second via structures extend only partially through the substrate thickness with thinner insulation layers to provide low capacitance and resistance for efficient signal transmission. This segmentation allows each via type to be optimized for its specific electrical function while maintaining overall connectivity.
3Reliability
If via structures are placed close to integrated circuit elements, then connectivity is improved, but noise coupling increases
Solution Approach 1:
The patent uses the insulation layer as an intermediary element between the via structures and integrated circuit elements. The first via structures are positioned adjacent to integrated circuit elements with thicker insulation layers that act as mediators to provide electrical isolation and noise shielding. This intermediary insulation layer allows the via structures to maintain close proximity to circuit elements for connectivity while simultaneously blocking noise coupling through their greater thickness and higher capacitance characteristics.
Data Source
AI summary
The present disclosure provides a semiconductor chip. In some embodiments, a semiconductor chip includes a semiconductor substrate, an integrated circuit layer formed on the semiconductor substrate, and a plurality of metal wiring layers sequentially formed on the semiconductor substrate and the integrated circuit layer. The semiconductor chip further includes a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the semiconductor substrate. The semiconductor chip further includes a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the semiconductor substrate.