Through-Electrode Via Geometry for Faster Semiconductor Signal Transfer

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor devices face challenges in achieving reliable electrical connections and efficient signal transfer due to the limitations of conventional solder balls and solder bumps, particularly in high-integration designs where smaller transistors lead to increased power consumption and reduced operating characteristics.

Innovation Solution

The semiconductor device incorporates a through electrode that penetrates the substrate and interlayer dielectric layer, with a unique wiring pattern design featuring vias with varying aspect ratios to enhance electrical connectivity, including a first via with a circular shape and a second via with a bar shape, arranged in rows and columns to provide a large contact area and low contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional solder balls or solder bumps are used for electrical connection, then the manufacturing process is simple, but the signal transfer speed is slow and electrical reliability is poor

Engineering Contradiction:
Improvesignal transfer speedVSAvoidthrough electrode structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The electrical connection path is segmented into multiple components: a through electrode penetrating the substrate, multiple interlayer dielectric layers with embedded wiring patterns, and vias connecting different levels. This segmentation allows each component to be optimized independently while achieving high-speed signal transfer through the combined structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a simple surface-mounted solder connection to a three-dimensional through-electrode structure that penetrates the substrate vertically and connects to multiple wiring layers at different heights, utilizing the vertical dimension to achieve shorter signal paths and faster transfer speeds.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the transistor size is reduced to achieve high integration, then the device density increases, but the power consumption increases and operating characteristics deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The invention replaces conventional solder-based electrical connections with a through-electrode structure integrated into multiple wiring layers, reducing contact resistance and improving electrical efficiency. This substitution lowers power consumption while maintaining high integration density.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If a simple contact structure is used, then the manufacturing process is easier, but the contact resistance is high and electrical characteristics are poor

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidwiring pattern fabrication complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention applies different structural characteristics to different parts of the electrical connection system: the through electrode provides a low-resistance vertical path through the substrate, while the embedded wiring patterns in interlayer dielectric layers provide controlled impedance pathways. Each region is optimized for its specific electrical function, achieving high reliability despite increased fabrication complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250014968A1Semiconductor device
Publication Date: 2025.01.09 SAMSUNG ELECTRONICS CO LTD
  • US20250014968A1 patent drawing
  • US20250014968A1 patent drawing
  • US20250014968A1 patent drawing

AI summary

A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.