Semiconductor Interconnect Layout Using Through-Vias for Dense 3D Cells
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Solution Overview
Problem
The arrangement of transistors in a vertical direction in semiconductor devices increases the diameter and depth of wirings, making it difficult to achieve high integration.
Innovation Solution
A semiconductor device design with transistors arranged in a vertical direction, featuring an interconnection structure that includes first and second through vias on the interface regions, connected by first and second wiring groups, reducing the horizontal area required for wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are arranged in a vertical direction, then integration density is improved, but wiring diameter and depth increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring structures including through-vias that extend vertically through multiple transistor layers. This dimensional change allows wirings to connect vertically stacked transistors without increasing horizontal area, resolving the contradiction between vertical transistor arrangement and wiring volume
2Quantity of substance
If transistors are arranged in a vertical direction, then integration density is improved, but horizontal area for wiring increases
Solution Approach 1:
The patent employs vertical through-vias and multi-layer interconnect structures that route signals in the vertical dimension rather than expanding horizontally. This allows dense vertical transistor stacking while maintaining compact horizontal footprint
3Reliability
If wiring diameter and depth are increased to connect vertically arranged transistors, then electrical connectivity is maintained, but manufacturing difficulty increases
Solution Approach 1:
The patent divides the wiring system into segmented components including through-vias, interlayer connectors, and horizontal wirings distributed across multiple layers. This segmentation allows each component to be formed using optimized processes, reducing overall manufacturing complexity despite the three-dimensional structure
Data Source
AI summary
A semiconductor device includes first cell transistors on a first cell region, second cell transistors on a second cell region spaced apart from the first cell region in a first direction, a first wiring group electrically connecting at least some of the first cell transistors to each other, a second wiring group electrically connecting at least some of the second cell transistors to each other. The first and second cell regions may be equal in size. The first wiring group may include a first through via and first wirings contacting upper and lower portions of the first through via. The second wiring group may include a second through via and second wirings contacting upper and lower portions of the second through via. Each of the first and second through vias may be on a center of a first interface region between the first and second cell regions.