Semiconductor Structure Ti Seed Layer Etching
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Solution Overview
Problem
In semiconductor chip manufacturing, the diffusion of titanium (Ti) atoms into dielectric layers during the formation of Ti metal seed layers can lead to short circuits, reducing the reliability of devices, especially in high I/O chip packages that require multiple layers of redistribution metal wires with precise line width and depth.
Innovation Solution
A method involving the formation of a Ti metal seed layer, a Cu metal seed layer, and subsequent wet etching processes to create grooves in the dielectric layer, ensuring the removal of interfacial Ti metal seed layers and preventing short circuits by establishing a depth difference between the grooves and the Ti metal seed layer, thereby enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a Ti metal seed layer is formed on the dielectric layer, then the dielectric layer can be etched selectively, but Ti atoms diffuse into the dielectric layer causing short circuits
Solution Approach 1:
The patent divides the Ti metal seed layer into two distinct parts: an upper Ti layer and an interfacial Ti layer. The upper Ti layer serves as the functional seed layer for Cu deposition, while the interfacial Ti layer acts as a diffusion barrier between the dielectric layer and the upper Ti layer. This segmentation allows selective etching of the upper Ti layer without removing the interfacial barrier layer, thus preventing Ti diffusion into the dielectric layer and avoiding short circuits.
2Productivity
If the Ti metal seed layer is removed by wet etching, then the dielectric layer is exposed, but remaining Ti atoms in the dielectric layer can cause short circuits
Solution Approach 1:
The patent performs a preliminary action by forming the interfacial Ti layer before depositing the upper Ti layer. This interfacial layer is specifically designed to remain after wet etching removes the upper Ti layer. The preliminary formation of this barrier layer ensures that when subsequent wet etching occurs, Ti atoms are prevented from diffusing into the dielectric layer, thus maintaining device reliability while allowing efficient etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes interfacial Ti metal seed layers, preventing short circuits and improving the reliability of semiconductor devices by creating a controlled depth difference in the grooves, which aids in avoiding potential short circuits and ensuring better performance.
Implementation Method 1
applying a first wet etching to remove the Ti metal seed layer to expose the dielectric layer; applying a second wet etching to remove the interfacial Ti metal seed layer
Implementation Method 2
When forming the Ti metal seed layer, a small amount of Ti will diffuse into the dielectric layer. Therefore, when the Ti metal seed layer is removed by wet etching, some titanium atoms from the Ti metal seed layer will remain in the dielectric layer, and the remaining Ti metal seeds have the potential to cause a short circuit
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method at least includes: applying a first wet etching to remove a Ti metal seed layer to expose a dielectric layer; performing a first pretreatment on the dielectric layer; forming a first groove in the dielectric layer to expose an interfacial Ti metal seed layer in the dielectric layer; applying a second wet etching to remove the interfacial Ti metal seed layer; and performing a second pretreatment on the dielectric layer to form a second groove with a depth greater than that of the interfacial Ti metal seed layer, which can effectively remove the interfacial Ti metal seed layer, and results in a depth difference between the bottom of the second groove and the interfacial Ti metal seed layer, thereby avoiding short circuits caused by the interfacial Ti metal seed layer, and improving device reliability.