Semiconductor Communication Timing Control Circuit for Non-Integer Clock Ratios
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Solution Overview
Problem
Existing communication systems between circuits with different clock frequencies face limitations in clock frequency ratios, leading to increased power consumption, nondeterministic operations, high communication latency, and reliability issues due to metastability, especially with dynamic frequency scaling and asynchronous systems.
Innovation Solution
A semiconductor device and communication method that utilize a communication timing control circuit to generate a communication timing signal based on frequency ratio and phase relation information, allowing circuits to communicate synchronously even with non-integer clock frequency ratios, thereby enabling flexible clock frequency settings, decisive operations, and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous communication is used between circuits with different clock frequencies, then communication can be achieved when frequency ratio is one to an integer or an integer to one, but the clock frequency ratio is limited and cannot accommodate non-integer ratios
Solution Approach 1:
A communication timing control circuit is introduced as an intermediary between the first circuit (operating at frequency M/N times the second clock) and the second circuit (operating at the second clock frequency). This control circuit generates communication timing signals that coordinate the handshake protocol, enabling reliable synchronous communication even when the clock frequency ratio is non-integer (M:N where M and N are integers). The intermediary translates between the different clock domains without requiring direct integer ratio synchronization.
2Adaptability or versatility
If asynchronous system is used to allow different clock frequencies, then clock frequency flexibility is improved, but communication latency increases and metastability issues occur
Solution Approach 1:
The communication protocol is segmented into distinct phases: request phase, acknowledgment phase, and data transfer phase. The communication timing control circuit generates separate timing signals for each phase (request timing signal, acknowledgment timing signal, data timing signal), allowing precise control of when each operation occurs. This segmentation enables the system to maintain synchronous communication benefits (low latency, no metastability) while accommodating non-integer clock frequency ratios through phased coordination rather than continuous asynchronous operation.
3Use of energy by moving object
If dynamic frequency scaling is implemented to reduce power consumption, then energy efficiency is improved, but clock frequency ratio limitations restrict the ability to scale frequencies freely
Solution Approach 1:
The communication timing control circuit is designed to dynamically adapt to changing clock frequency ratios. It receives frequency ratio information as input and dynamically generates appropriate communication timing signals based on the current M:N ratio between the first and second clocks. This dynamic capability allows circuits to freely scale their operating frequencies for power optimization while the communication interface automatically adjusts to maintain reliable synchronous communication at any supported frequency combination.
4Ease of operation
If counter circuit is used to generate communication timing signal based on frequency ratio information, then timing control is achieved, but the system requires precise integer ratio relationships
Solution Approach 1:
The communication timing control circuit is designed with universal functionality to handle multiple frequency ratio scenarios. It accepts frequency ratio information indicating an M:N relationship (where M and N are integers) between the first clock frequency and the second clock frequency. The circuit universally generates appropriate communication timing signals regardless of the specific M:N ratio, making the system adaptable to various frequency combinations while maintaining precise timing control through the standardized handshake protocol interface.
Data Source
AI summary
It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit. The communication timing control circuit generates the communication timing signal determined by a frequency ratio information and a phase relation information, the frequency ratio information setting a frequency ratio of the first clock signal to the second clock signal, the phase relation information indicating a phase relation between the first clock signal and the second clock signal.