Semiconductor Device Timing Synchronization for Video Signal Processing

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Solution Overview

Problem

Conventional semiconductor devices face issues with image disturbance in display panels due to mismatches in timing state transitions during operation mode changes, leading to incorrect processing of video signals as non-video data or vice versa.

Innovation Solution

A semiconductor device with a receiving circuit, logic circuit, detecting circuit, measuring circuit, and determining circuit that processes communication frames with different periods, allowing the logic circuit to transition between operation states based on the detected period, ensuring accurate processing of video signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the operation mode of a semiconductor device changes to receive video signals, then the device can process high-speed video data, but timing mismatches may cause non-video data to be incorrectly processed as video signals

Engineering Contradiction:
Improvevideo signal processing capabilityVSAvoiddata processing accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The transmitting side performs preliminary actions by sending a mode change notification before actually switching to video signal transmission mode. The receiving side waits for this notification and only transitions to video reception mode after receiving it, ensuring both sides are synchronized and preventing timing mismatches that would cause data processing errors.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If high-speed transmission is implemented for uncompressed video signals, then display resolution and frame rates increase, but timing synchronization between devices becomes more critical and error-prone

Engineering Contradiction:
Improvedisplay resolution and frame rateVSAvoidtiming synchronization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system implements feedback through mode change notifications sent from the transmitting side to the receiving side. This feedback mechanism ensures that the receiving side is aware of the mode transition timing and can synchronize its operations accordingly, maintaining reliable timing synchronization even during high-speed transmission of uncompressed video signals.

Inventive Principle:
Principle #23Feedback

3Speed

If the receiving side transitions to video reception mode before the transmitting side, then video signals can be received, but the data may be incorrect as the transmitter is still in non-video mode

Engineering Contradiction:
Improveresponse speed of mode transitionVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The transmitting side performs the preliminary action of sending a mode change notification before actually switching to video transmission mode. The receiving side waits for this notification and only transitions to video reception mode after receiving it, ensuring that the receiving side does not transition before the transmitting side and preventing data integrity errors.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10460654B2Semiconductor device and display apparatus
Publication Date: 2019.10.29 MAGNOLIA BLUE CORP
  • US10460654B2 patent drawing
  • US10460654B2 patent drawing
  • US10460654B2 patent drawing

AI summary

A semiconductor device includes: a receiving circuit which receives communication frames each transmitted with a first period or a second period that are different from each other and including a synchronization code and data; a logic circuit which has a first operation state in which the received communication frames are each processed as data other than a digital video signal, and a second operation state in which the received communication frames are each processed as the digital video signal; a detecting circuit which detects the synchronization code from each of the received communication frames; a measuring circuit which measures a period of the detected synchronization code; and a determining circuit which determines the measured period. The logic circuit substantially makes a transition to the first operation state or the second operation state according to a result of the determining.