Semiconductor Circuit Design Using Topographical Rules
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Solution Overview
Problem
Conventional semiconductor chip design relies on simplistic models leading to inaccuracies due to one-dimensional analysis, resulting in suboptimal design rules and reduced yields, as the complex shapes of features on wafers are not accurately represented.
Innovation Solution
The implementation of Topographical Design Rules (TDRs) and Monte Carlo simulations using advanced photolithography and process variability band analysis to derive more accurate and complex shape representations, allowing for rigorous evaluation of design space and optimized design rules that account for variations in feature dimensions and spatial relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simple geometric models are used for design analysis, then the analysis process is simple and fast, but the accuracy of feature shape representation is poor
Solution Approach 1:
The patent transitions from one-dimensional analysis (considering only critical dimension tolerances) to two-dimensional analysis by incorporating shape descriptors that capture angular information and geometric complexity. This dimensional expansion enables accurate representation of complex feature shapes while maintaining computational feasibility through systematic mathematical formulations.
Solution Approach 2:
The patent introduces shape descriptors as additional parameters beyond traditional critical dimensions. These descriptors include angular measurements and geometric characteristics that fundamentally change the parameter set used in design analysis, enabling precise characterization of complex shapes without requiring full two-dimensional imaging or excessively complex models.
2Productivity
If conventional one-dimensional analysis is used, then the design process is simple, but the yield and die size positioning are suboptimal
Solution Approach 1:
The patent implements a feedback mechanism where shape descriptors derived from actual manufactured features are used to refine and update design rules. This closed-loop approach continuously improves the accuracy of design space assessment by incorporating real manufacturing data, leading to optimized yield and die size positioning through iterative refinement of design parameters.
Solution Approach 2:
The patent performs preliminary characterization of feature shapes using shape descriptors before final design rule establishment. By预先 analyzing the geometric characteristics and angular properties of manufactured features, the system proactively identifies optimal design parameters that will maximize yield and achieve accurate die size positioning before full-scale production begins.
3Manufacturing precision
If simplistic shape models are assumed, then the manufacturing process is easier to control, but errors of several to tens of nanometers occur
Solution Approach 1:
The patent applies local quality by using shape descriptors to characterize specific local geometric features such as corners and edges individually. Rather than applying a uniform simple model to all features, the system captures the unique geometric characteristics of each feature type, enabling precise control of local manufacturing variations while maintaining overall process simplicity through standardized measurement approaches.
Data Source
AI summary
The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.