Semiconductor Trace Memory Utilization via Dynamic Bus Access

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Solution Overview

Problem

Existing semiconductor devices require a dedicated trace memory to implement real-time trace functions, leading to increased costs.

Innovation Solution

A semiconductor device configuration that includes a microprocessor, instruction memory, data memory, and buses, where trace information is output and written into the data memory during periods when the microprocessor does not access the data memory, eliminating the need for a dedicated trace memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated trace memory is provided to hold trace information, then real-time trace function is achieved, but cost increases

Engineering Contradiction:

Improvereal-time trace functionVSAvoidcost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The data memory is designed to serve dual purposes: storing data items during normal microprocessor operation and storing trace information when the microprocessor does not access it. This multi-functional approach eliminates the need for a separate dedicated trace memory, thereby reducing cost while maintaining real-time trace capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically switches the function of the data memory between storing data items and storing trace information based on the microprocessor's access patterns. When the microprocessor does not access the data memory during branch instruction execution, the memory dynamically transitions to store trace information, optimizing resource utilization.

Inventive Principle:

Principle #15Dynamics

2Productivity

If trace information is written into data memory during microprocessor access periods, then memory resource utilization increases, but data access reliability decreases

Engineering Contradiction:

Improvememory resource utilizationVSAvoiddata access reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system uses periodic timing signals (H0, H1, H2, H3) to control when trace information is written to the data memory. Writes occur during specific periods when the microprocessor does not access the data memory, creating a periodic pattern that prevents conflicts between trace information writing and microprocessor data access, thereby maintaining data access reliability while improving memory utilization.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9032255B2Semiconductor device and control method thereof

Publication Date: 2015.05.12 RENESAS ELECTRONICS CORP

AI summary

Provided is a semiconductor device including: a first memory that stores multiple instructions; a second memory that stores multiple data items; first and second buses; a microprocessor that fetches, through the first bus, an instruction at a specified address among the multiple instructions stored in the first memory, executes the instruction, and accesses the second memory through the second bus based on a result of the execution; and a trace information output unit that acquires, when a branch instruction is generated in the microprocessor, address information of the first memory specified before branching, and outputs the information as trace information. The trace information output from the trace information output unit is written into the second memory through the second bus in a period in which the microprocessor does not access the second memory during execution of the branch instruction.