Semiconductor Training System Using Segmented Memory Bank and Pipe Register Operations
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Solution Overview
Problem
Current semiconductor systems face challenges in reducing training time and improving accuracy during signal training operations between masters and slaves, particularly in efficiently writing and reading test data across memory banks.
Innovation Solution
The semiconductor system incorporates a master that writes test data to multiple unit memory regions, reads the data, and determines a pass/fail result, utilizing a data path switching circuit and control circuit to manage data transmission timing and reference voltage, allowing for direct writing and reading of test data without intermediate processes, thereby reducing training time and increasing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If test data is written to memory banks through conventional training operations, then the training function can be performed, but the training time is excessive and the process is complex
Solution Approach 1:
The patent segments the training operation into two distinct training modes: first training operation that writes test data to memory banks, and second training operation that writes test data to pipe registers. This segmentation allows selective execution of training steps, reducing overall training time while maintaining comprehensive training coverage.
Solution Approach 2:
The patent implements preliminary action by performing a first training operation to write test data to memory banks before the second training operation. The control circuit determines whether to execute the second training operation based on the results of the first training operation, allowing early termination if training is already successful, thus reducing training time.
2Measurement precision
If test data is written to memory banks and read back for training, then training accuracy can be maintained, but the number of read/write operations increases training time
Solution Approach 1:
The patent applies dynamics by making the training operation flexible and adaptive. The control circuit dynamically determines whether to perform the second training operation based on results from the first training operation. This dynamic adjustment optimizes the balance between training accuracy and training time by avoiding unnecessary redundant operations.
Solution Approach 2:
The patent changes operational parameters by introducing two different training modes with different data storage locations (memory banks vs. pipe registers). The system can switch between these modes or combine them based on training requirements, allowing optimization of both accuracy and time by selecting the appropriate training parameter configuration.
3Productivity
If direct writing and reading of test data is implemented without intermediate processes, then training time is reduced, but data transmission control becomes more complex
Solution Approach 1:
The control circuit is designed with multi-functionality to handle both first and second training operations, manage data paths to memory banks and pipe registers, and determine when to execute each operation based on training results. This universal control structure manages the complexity of direct data transmission while enabling flexible training operation selection.
Solution Approach 2:
The control circuit acts as an intermediary that manages the complex data transmission control. It receives commands, determines which training operation to perform, controls data writing to appropriate storage locations, and manages the read-back process. This intermediary approach consolidates control logic, making the complex data path management more organized and manageable.
Data Source
AI summary
A semiconductor system includes a slave including a plurality of unit memory regions. The semiconductor system further includes a master configured to perform a training operation by writing test data to the plurality of unit memory regions, reading the written test data, and determining a pass/fail result for the read test data.