Semiconductor Transformer With Substrate-Embedded Coils
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Solution Overview
Problem
High power semiconductor transformers face challenges in conducting large currents while maintaining a compact footprint, as increasing metal layer thickness for high current handling results in increased size and thermal dissipation issues.
Innovation Solution
A semiconductor transformer design featuring a first and second coil inductor with a substrate-embedded structure, utilizing a low-k isolation block and core block elements to enhance thermal dissipation and reduce size, with conductive elements bridging the coils without physical contact to maintain efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metal layer thickness is increased to conduct large current, then current handling capability is improved, but thermal dissipation deteriorates and device size increases
Solution Approach 1:
The patent transitions from planar surface mounting to three-dimensional substrate embedding. Coil inductors are formed within trenches etched into the substrate, allowing current paths to extend through the substrate thickness rather than only across the surface. This vertical dimension enables longer effective conductor length and better current distribution without increasing planar footprint, thereby improving current handling while maintaining compact size and facilitating thermal dissipation through the substrate.
Solution Approach 2:
The patent embeds coil inductors within substrate trenches, creating a nested structure where conductive elements are positioned within recesses in the substrate. This nesting approach allows multiple functional layers (coils, insulation, contacts) to be integrated within the substrate volume, increasing effective current path length without proportionally increasing external dimensions, thus improving power handling while controlling device size.
2Power
If metal layer thickness is increased to conduct large current, then current handling capability is improved, but device footprint area increases
Solution Approach 1:
The patent utilizes the substrate thickness dimension by etching trenches and forming coils within the substrate volume rather than spreading conductors across the surface. This vertical integration allows the effective current-conducting path length to increase with substrate thickness rather than footprint area, enabling high current handling in a compact planar footprint.
3Power
If trace width is increased to handle high current, then current handling capability is improved, but transformer size increases
Solution Approach 1:
The patent forms coil inductors within substrate trenches, utilizing the vertical dimension (substrate thickness) to provide extended current paths. This allows the transformer to handle high currents through three-dimensional current distribution rather than increasing two-dimensional trace width, thereby maintaining compact transformer volume while achieving high power capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced DC resistance and improved thermal dissipation, enabling high current handling capability and compact integration, while minimizing eddy currents and parasitic capacitance for enhanced performance.
Implementation Method 1
A transformer can transmit energy from one circuit to another circuit via electromagnetic coupling
Implementation Method 2
the metal layer thickness may not be able to conduct large current with good thermal dissipation
Data Source
AI summary
A semiconductor transformer includes a first coil inductor and a second coil inductor. The first coil inductor has a first port, a second port and a first coil inductor wall, the first coil inductor wall having a height substantially equal to a thickness of the substrate. The second coil inductor has a third port, a first extension wall connected to the third port, a fourth port, a second extension wall connected to the fourth port and a second coil inductor wall.