3D Semiconductor Transistor Placement via Direct-Write eBeam
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Solution Overview
Problem
The increasing cost of mask sets and limited flexibility in semiconductor fabrication, particularly for custom products, due to the need for multiple expensive mask sets to accommodate varying device designs and higher data transfer rates, lead to high development costs and inefficient use of silicon area in FPGA technologies.
Innovation Solution
The use of re-programmable antifuse technology in conjunction with Through Silicon Via (TSV) to construct configurable logic devices, allowing for the placement of transistors above or below antifuse configurable interconnect circuits, which reduces the need for antifuse programming logic and enhances silicon area utilization, and enables modular construction of configurable systems with improved vertical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple expensive mask sets are used to accommodate varying device designs, then design flexibility is improved, but manufacturing cost increases exponentially
Solution Approach 1:
The patent segments the semiconductor fabrication process into multiple layers, with generic layers fabricated using shared mask sets and custom layers fabricated using direct-write eBeam technology. This allows the majority of the device structure to be produced cost-effectively while enabling customization in specific regions without requiring complete mask sets for each design variation.
Solution Approach 2:
The patent introduces direct-write eBeam fabrication as an additional dimensional approach to traditional mask-based photolithography. This alternative fabrication dimension enables direct patterning of custom layers without requiring physical mask sets, thereby decoupling design flexibility from mask set costs.
2Manufacturing precision
If dedicated mask sets are created for each Master Slice, then customization precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent creates a universal fabrication approach where a single mask set can be used across multiple Master Slice designs for generic layers. The direct-write eBeam capability provides universal customization precision for custom layers regardless of the specific Master Slice configuration, eliminating the need for dedicated mask sets for each design.
Solution Approach 2:
The patent uses direct-write eBeam technology to copy and paste custom patterns directly onto the semiconductor substrate without requiring physical mask copies. This digital-to-physical copying approach maintains customization precision while eliminating the complexity of managing multiple physical mask sets.
3Ease of manufacture
If transistors are placed only in the silicon substrate, then manufacturing simplicity is maintained, but silicon area utilization decreases
Solution Approach 1:
The patent extends the transistor placement from the traditional two-dimensional silicon substrate plane to the third dimension by fabricating transistors above the substrate using direct-write eBeam technology. This vertical expansion of the fabrication dimension increases silicon area utilization while maintaining manufacturing simplicity through a unified fabrication approach.
4Adaptability or versatility
If antifuse programming logic is extensively used, then configurability is improved, but silicon area consumption increases
Solution Approach 1:
The patent extracts the antifuse programming logic from the silicon substrate and implements it in a separate custom layer fabricated using direct-write eBeam technology. This separation removes the bulk of the programming logic from the substrate, reducing silicon area consumption while preserving full configurability through the custom layer.
Data Source
AI summary
A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact is aligned to the first transistors with less than about 40 nm alignment error, a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.