Semiconductor Structure With Series-Connected Transistor and Resistor

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Solution Overview

Problem

The manufacturing and integration of semiconductor devices are complex, leading to issues such as insufficient sheet resistance in miniaturized resistors, which necessitates an improvement in the manufacturing process to address these challenges.

Innovation Solution

A semiconductor structure is formed with a series-connected transistor and resistor using a shared process flow, where the gate electrode and resistor electrode are formed in the semiconductor substrate with an isolation structure between them, allowing for high sheet resistance without additional masks or process steps, thereby reducing costs and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If conventional process flow is used to form miniaturized resistors, then device size is reduced, but sheet resistance becomes insufficient

Engineering Contradiction:
Improvedevice sizeVSAvoidsheet resistance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent merges the formation of the resistor electrode with the gate electrode into a single process step. Both electrodes are formed simultaneously from the same electrode layer, eliminating the need for separate masking and deposition steps for the resistor. This integration allows the resistor to achieve high sheet resistance through the inherent properties of the electrode material and geometry, while maintaining miniaturized device dimensions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The electrode layer serves multiple functions: it forms both the gate electrode for the transistor and the resistor electrode for the resistor. This multi-functional approach allows a single material deposition step to create both critical components, ensuring consistent material properties and achieving the desired high sheet resistance in the resistor without requiring additional specialized processing steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional masks or process steps are used to achieve high sheet resistance, then resistor performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvesheet resistanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of gate electrode and resistor electrode is merged into a single process step using one mask pattern. The electrode layer is deposited and patterned once to create both structures, eliminating the need for separate masking, deposition, and etching steps that would otherwise be required to achieve high sheet resistance in the resistor.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The same electrode layer and masking process serve dual purposes: defining the gate electrode geometry for transistor operation and defining the resistor electrode geometry for high sheet resistance. This universal approach uses the inherent electrical properties of the electrode material to achieve both transistor gate functionality and high-resistance resistor functionality without additional process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11621198B2Semiconductor structure implementing series-connected transistor and resistor and method for forming the same
Publication Date: 2023.04.04 NAN YA TECH
  • US11621198B2 patent drawing
  • US11621198B2 patent drawing
  • US11621198B2 patent drawing

AI summary

A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.