Semiconductor Device with Orthogonal Transistor Rows and Inner Collector Bump
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Solution Overview
Problem
Semiconductor devices with heterojunction bipolar transistors experience increased parasitic inductance and resistance in collector or drain current paths, leading to decreased maximum output in power amplification circuits.
Innovation Solution
The semiconductor device is designed with two transistor rows arranged orthogonally, featuring a first wiring between the rows and at least one bump overlapping with the wiring, connected to the collectors or drains, which reduces parasitic inductance and resistance by increasing the current path cross-section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the collector wiring is arranged between the two transistor rows and the collector bump is arranged in the outer side portion, then the transistor rows can be arranged in parallel, but the parasitic inductance and parasitic resistance in the collector current path increase
Solution Approach 1:
The patent moves the collector bump from the outer side portion to the inner side region between the two transistor rows. This dimensional repositioning changes the current path geometry, allowing the collector current to flow perpendicular to the transistor row arrangement direction, thereby reducing the effective path length and minimizing parasitic inductance and resistance while maintaining the parallel transistor row configuration.
2Ease of manufacture
If the collector current flows through the collector wiring in the array direction of the transistors, then the wiring layout is simplified, but the parasitic inductance and parasitic resistance increase
Solution Approach 1:
Instead of arranging the collector bump in the conventional outer side position and having current flow in the array direction, the patent inverts this arrangement by placing the collector bump in the inner region between transistor rows. This inversion causes the collector current to flow in the opposite direction (perpendicular to array direction), which reduces the current path length and minimizes parasitic effects while still maintaining manufacturing simplicity.
Data Source
AI summary
Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.