Semiconductor Transistor Layout to Reduce Dielectric Stress Leakage
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Solution Overview
Problem
High voltage or medium voltage power devices with large oxide diffusion areas face increased crystal defects and current leakage due to manufacturing stresses, which affect their reliability.
Innovation Solution
A semiconductor structure is designed with a dielectric element misaligned with highly doped regions and a gate structure that forms a channel away from the dielectric element, reducing stress and preventing dielectric-induced defects during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If large oxide diffusion area is used in high voltage or medium voltage power devices, then the device can bear high applied voltage or medium applied voltage, but crystal defects which may induce current leakage increase due to manufacturing stresses
Solution Approach 1:
The patent applies local quality by creating a stress relief structure specifically at the oxide diffusion region where manufacturing stresses concentrate. The relief structure is localized to the area experiencing highest stress (the oxide diffusion region) rather than modifying the entire device, allowing the large oxide diffusion area to maintain its voltage bearing capability while locally reducing crystal defects and current leakage in the critical stress zone
Solution Approach 2:
The patent segments the oxide diffusion region by introducing a relief structure that divides the continuous oxide diffusion area into distinct zones. This segmentation allows the stress to be distributed and managed in specific regions, preventing the accumulation of crystal defects while maintaining the overall large oxide diffusion area needed for high voltage bearing capability
2Strength
If large oxide diffusion area is used in power devices, then high voltage or medium voltage bearing capability is achieved, but manufacturing stresses increase causing crystal defects
Solution Approach 1:
The patent applies beforehand cushioning by pre-introducing a stress relief structure into the oxide diffusion region before manufacturing processes complete. This relief structure acts as a cushion that absorbs and distributes manufacturing stresses before they can cause crystal defects, protecting the large oxide diffusion area from stress-induced damage while maintaining voltage bearing capability
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.