Semiconductor Scribe Lane Trench for Chip Crack Containment
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Solution Overview
Problem
Cracks generated in the scribe lane region during the cutting process of semiconductor substrates can spread into semiconductor chips, causing errors in the chips.
Innovation Solution
A semiconductor device with a dam structure, dielectric layer, insulating interlayer, conductive pattern, and photosensitive insulation layer, featuring a trench in the scribe lane region that exposes the dam structure and includes a crack-blocking layer and crack-blocking portion to prevent crack spread into chip regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor substrate is cut along the scribe lane region to singulate the semiconductor chips, then the semiconductor chips can be separated into independent chips, but cracks may be generated in the scribe lane region and spread into the semiconductor chips causing errors
Solution Approach 1:
The patent divides the scribe lane region into multiple segments by forming a trench that extends through the insulating interlayer and dielectric layer. This segmentation creates separate zones that prevent crack propagation from one area to another, while still allowing the substrate to be cut and chips to be singulated effectively.
Solution Approach 2:
The patent introduces a crack-blocking layer as an intermediary structure formed on the inner surface of the trench. This layer acts as a mediator that blocks crack propagation paths between the scribe lane region and the chip regions, preventing cracks generated during cutting from spreading into the semiconductor chips.
2Reliability
If a trench is formed to extend through the insulating interlayer and dielectric layer to expose the dam structure, then crack spread can be blocked, but the device structure becomes more complex
Solution Approach 1:
The patent addresses the complexity issue by extending the trench in the vertical dimension through multiple layers (insulating interlayer and dielectric layer) rather than creating complex lateral structures. This vertical extension effectively blocks crack propagation while maintaining a relatively simple overall structure that integrates with existing device layers.
Solution Approach 2:
The crack-blocking layer is nested within the trench structure, and the trench itself is nested within the existing device architecture alongside the dam structure. This nesting approach allows the crack-blocking functionality to be integrated into the existing device structure without requiring completely separate complex systems.
Data Source
AI summary
A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.