Semiconductor Device Trench Control Gate Capacitance
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in reducing the area of memory cells while maintaining sufficient capacity, particularly in single-layer polysilicon type memories where increasing the capacitance of the control gate leads to larger unit areas.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with trenches in the control gate well region, a conductive layer extending across the insulating film, and a gate polysilicon layer, allowing for increased capacitance without expanding the horizontal area, thereby reducing the memory cell size while maintaining capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the control gate overlapping with the floating gate is increased to increase the capacitance of the control gate, then the capacitance of the control gate is improved, but the unit area of the memory cell increases
Solution Approach 1:
The patent introduces a third dimension by forming a trench in the control gate well region and filling it with conductive material. This vertical structure increases the overlapping area between the control gate and floating gate without expanding the horizontal footprint of the memory cell, thereby increasing capacitance while maintaining compact cell area
Solution Approach 2:
The conductive material is nested within the trench structure formed in the control gate well region. This nested configuration allows the control gate to extend vertically into the substrate, increasing the effective overlapping area with the floating gate without occupying additional horizontal space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the capacitance of the control gate relative to the read and tunnel gates, enabling efficient data writing and erasure operations with a smaller memory cell area, ensuring effective electric potential management.
Implementation Method 1
Capacitors corresponding to the floating gate, the read gate, and the tunnel gate are formed at parts opposed to the floating gates with the respective gate insulating films of the first well region, second well region, and third well region interposed therebetween
Data Source
AI summary
A semiconductor device constituting a non-volatile memory includes a semiconductor portion of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, an insulating film, and a conductive layer. The first well includes a trench extending from the surface of the semiconductor portion to an inside of the first well. The insulating film extends on a surface inside the trench. A conductive portion formed continuous with the conductive layer is disposed on the insulating film inside the trench.