Semiconductor Device Trench Depth Control via Segmented Etching

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Solution Overview

Problem

Current semiconductor fabrication methods face challenges in forming cell and peripheral device isolation patterns to specific depths without being affected by etch loading effects, which can lead to crystal defects and compromised electric characteristics.

Innovation Solution

The method involves forming preliminary trenches in the cell and boundary regions followed by separate etching processes to create cell and peripheral trenches, allowing for controlled depth formation and reducing etch loading effects, thereby enabling the formation of cell and peripheral device isolation patterns with improved precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate etching processes are used to form cell and peripheral trenches, then manufacturing precision of trench depth is improved, but device complexity increases

Engineering Contradiction:
Improvetrench depth precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into separate etching operations: first etching cell trenches to a first depth, then etching peripheral trenches to a second depth. This segmentation allows each trench type to be etched independently to its specific required depth, achieving precise depth control for both cell and peripheral regions without mutual interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Cell trenches are etched first to the required depth before peripheral trenches are etched. This preliminary action ensures that the cell trench depth is established and protected from subsequent processing, while the peripheral trenches are then etched to their specific depth without affecting the already-formed cell trenches.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If etch loading effects are avoided through separate etching processes, then reliability of electric isolation is improved, but loss of time in fabrication increases

Engineering Contradiction:
Improveelectric isolation reliabilityVSAvoidfabrication time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The etching process is divided into separate operations for cell and peripheral trenches, preventing etch loading effects that would occur if all trenches were etched simultaneously. This segmentation ensures each trench type reaches its target depth without being hindered by the presence of other trenches, achieving reliable electric isolation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The fabrication process maintains continuous progress by sequentially etching cell trenches first, then immediately etching peripheral trenches without unnecessary interruptions. This continuous approach minimizes total fabrication time while ensuring each etching operation completes fully before the next begins, avoiding the time loss associated with rework or defect correction.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11430795B2Semiconductor device and method of fabricating the same
Publication Date: 2022.08.30 SAMSUNG ELECTRONICS CO LTD
  • US11430795B2 patent drawing
  • US11430795B2 patent drawing
  • US11430795B2 patent drawing

AI summary

A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region therebetween, a cell device isolation pattern on the cell region of the substrate to define cell active patterns, a peripheral device isolation pattern on the peripheral region of the substrate to define peripheral active patterns, and an insulating isolation pattern on the boundary region of the substrate, the insulating isolation pattern being between the cell active patterns and the peripheral active patterns, wherein a bottom surface of the insulating isolation pattern includes a first edge adjacent to a side surface of a corresponding one of the cell active patterns, and a second edge adjacent to a side surface of a corresponding one of the peripheral active patterns, the first edge being at a height lower than the second edge, when measured from a bottom surface of the substrate.