Semiconductor Trench Depth Optimization for On-Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in minimizing on-resistance due to the distance and area of carrier travel between doping regions, which affects the performance of the device.
Innovation Solution
A method and structure for forming semiconductor devices that include a substrate with a drift region, dielectric patterns, an isolation pattern, and well regions, where the depth of the first trench is less than the third trenches, allowing for a uniform bottom surface and reduced carrier drift length, thereby minimizing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the depth of the first trench is made equal to the depth of the third trenches, then the manufacturing process is simplified, but the cross-sectional area of the drift region is reduced and on-resistance increases
Solution Approach 1:
The patent divides the trench structure into two distinct types: first trenches with shallower depth formed in the transistor region, and third trenches with greater depth formed adjacent to the drift region. This segmentation allows each trench type to serve its specific function - the shallower first trenches simplify manufacturing while the deeper third trenches maintain adequate drift region cross-sectional area to minimize on-resistance.
Solution Approach 2:
The patent applies different trench depths at different locations within the semiconductor device. The first trenches in the transistor region have a first depth, while the third trenches adjacent to the drift region have a second depth greater than the first depth. This local differentiation optimizes both manufacturing ease and electrical performance in their respective regions.
2Ease of manufacture
If the isolation pattern is formed at the same depth as the dielectric patterns, then the manufacturing process is simplified, but the carrier drift length cannot be optimized and on-resistance is not minimized
Solution Approach 1:
The patent introduces a vertical depth dimension differentiation between the isolation pattern and the dielectric patterns. The isolation pattern is formed at a first depth while the dielectric patterns are formed at a second depth greater than the first depth. This vertical separation allows the isolation pattern to be positioned optimally to minimize carrier drift length through the drift region, while the deeper dielectric patterns provide adequate isolation, thereby resolving the contradiction between manufacturing simplicity and electrical performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach reduces the on-resistance of power MOS transistors by increasing the cross-sectional area of the drift region and optimizing the depth of the isolation pattern relative to the dielectric patterns, enhancing the performance of the semiconductor device.
Implementation Method 1
carriers, such as electrons or holes, travel through a channel between predetermined doping regions. The distance or area of travel of the carriers may affect on-resistance of the semiconductor device
Implementation Method 2
Forming the drift region may include implanting dopants of a first conductivity type into the substrate surrounding the first trench in the transistor region
Data Source
AI summary
A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.