Semiconductor Trench Device Gate Threshold Stability
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Solution Overview
Problem
As semiconductor devices are downscaled, the narrowing trench interval can cause the P+ layer to unexpectedly contact the trench portion, leading to an increase in gate threshold voltage.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with trench portions, an emitter region, and contact regions of alternating conductivity types, where the second contact region has a higher doping concentration and is strategically positioned to avoid contact with the emitter region, thereby maintaining a larger distance and reducing the impact on gate threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the trench interval is narrowed to downscale the semiconductor device, then the device size is reduced, but the P+ layer may contact the trench portion causing gate threshold voltage to increase
Solution Approach 1:
The patent introduces a vertical dimension solution by forming the second contact region at a depth smaller than the emitter region, separating the contact regions vertically rather than only horizontally. This dimensional change allows the contact regions to be positioned apart from the emitter region in the depth direction, preventing unwanted contact while maintaining planar layout density for downsizing.
Solution Approach 2:
The patent applies local quality by creating a second contact region with higher doping concentration than the first contact region, and positioning it specifically at a depth smaller than the emitter region. This localized modification of doping concentration and position allows the contact region to maintain electrical functionality while avoiding contact with the emitter region, thus preventing gate threshold voltage increase.
2Reliability
If the second contact region is positioned closer to the emitter region to improve electrical connection, then contact resistance is reduced, but gate threshold voltage fluctuates due to misalignment
Solution Approach 1:
By utilizing the depth dimension, the patent positions the second contact region vertically separated from the emitter region (at a depth smaller than the emitter region). This vertical separation provides a stable, misalignment-tolerant configuration that maintains consistent electrical connection without causing gate threshold voltage fluctuations, even when lateral positioning varies.
Solution Approach 2:
The patent changes the doping concentration parameter by making the second contact region have a higher doping concentration than the first contact region. This parameter change ensures low contact resistance for reliable electrical connection while the vertical positioning at reduced depth provides stability against misalignment, preventing gate threshold voltage fluctuations.
Data Source
AI summary
Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of first trench portions formed at a front surface side of the semiconductor substrate and extending in a predetermined extending direction in a planar view; an emitter region of a first conductivity type formed between adjacent trenches of the plurality of first trench portions at the front surface side of the semiconductor substrate; a first contact region of a second conductivity type formed between the adjacent trenches of the plurality of first trench portions, the first contact region and the emitter region being arranged alternately in the extending direction; and a second contact region of a second conductivity type formed above the first contact region to be apart from the emitter region and having a higher doping concentration than the first contact region.