Power Semiconductor Trench Layout for Higher ESD Robustness
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Solution Overview
Problem
Small power semiconductor chips often fail to provide sufficient Electrostatic Discharge (ESD) robustness, leading to design challenges that may increase costs or reduce device performance when addressing this issue through larger chip sizes or altered contact schemes.
Innovation Solution
Incorporating specialized trench structures with varying pitches in the edge termination and control terminal regions of the semiconductor device, allowing for improved ESD robustness without additional process steps or significant layout changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip size is increased to improve ESD robustness, then ESD robustness is improved, but device cost increases
Solution Approach 1:
The patent applies local quality by implementing a non-uniform trench pitch structure where the first pitch is used in the active region and a second pitch is used in the edge termination region. This localized structural variation optimizes ESD robustness specifically in the edge termination region without requiring an overall increase in chip size, thereby improving reliability while controlling manufacturing cost.
2Reliability
If the contact scheme of mesas and trenches is changed to improve ESD robustness, then ESD robustness is improved, but device performance is reduced
Solution Approach 1:
The patent implements local quality by differentiating the trench structure between the active region and edge termination region. The first pitch in the active region maintains optimal device performance, while the second pitch in the edge termination region enhances ESD robustness. This spatial differentiation allows simultaneous optimization of both performance and reliability without compromising either.
3Reliability
If the chip size is increased to improve ESD robustness, then ESD robustness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the chip into two functional regions with different trench characteristics: the active region with the first pitch and the edge termination region with the second pitch. This segmentation allows each region to be optimized independently for its specific function, achieving enhanced ESD robustness through structured differentiation rather than uniform scaling.
Solution Approach 2:
By implementing local quality through region-specific trench pitches, the patent achieves enhanced ESD robustness in the edge termination region without requiring a proportional increase in overall chip size. This localized optimization reduces manufacturing complexity compared to uniform chip scaling while maintaining the desired reliability improvement.
Data Source
AI summary
A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body; a second load terminal at a second side of the semiconductor body opposite the first side, the power semiconductor device configured to conduct a load current between the load terminals; a control terminal at the first side configured to receive a control signal for controlling the load current; within an active region at least partially surrounded by an edge termination region, first trenches laterally confining mesas for conducting the load current, having control trenches electrically connected to the control terminal, and arranged in accordance with a first average pitch; and in a region laterally overlapping the control terminal, second trenches arranged in accordance with a second average pitch different from the first average pitch and electrically connected to the control terminal.