Semiconductor Trench Etching to Reduce DRAM GIDL Leakage
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Solution Overview
Problem
Semiconductor structures, particularly dynamic random access memory (DRAM), suffer from gate-induced drain leakage (GIDL) due to damage to the insulating layer during the etching process of the conductive layer, leading to reduced yield and insulation weakness.
Innovation Solution
A method involving multiple etching processes is employed to control the removal of the first conductive layer, minimizing damage to the insulating layer and ensuring its thickness, thereby reducing GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching process is used to remove the conductive layer, then the manufacturing process is simple and fast, but the insulating layer is damaged and GIDL occurs
Solution Approach 1:
The single etching process is divided into multiple sequential etching processes with different etching depths and conditions. The first etching process removes the conductive layer to a first depth, and the second etching process removes it to a second depth greater than the first depth. This segmentation allows controlled removal that protects the insulating layer from damage while achieving complete conductive layer removal.
Solution Approach 2:
Different etching parameters are used in different etching processes. The first etching process uses parameters optimized for removing the conductive layer to a controlled depth, while the second etching process uses different parameters to remove the remaining conductive layer to the target depth. This parameter optimization minimizes damage to the insulating layer while maintaining etching efficiency.
2Device complexity
If the conductive layer is removed to a greater depth in one step, then the process is efficient, but the insulating layer thickness is reduced and insulation performance deteriorates
Solution Approach 1:
The etching process is segmented into multiple steps with progressively increasing depths. The first etching process removes the conductive layer to a first depth, preserving the insulating layer thickness. The second etching process then removes the remaining conductive layer to a second depth. This segmentation enables precise control of insulating layer thickness while achieving complete conductive layer removal.
Solution Approach 2:
The first etching process performs a preliminary removal of the conductive layer to a controlled depth before the second etching process. This preliminary action protects the insulating layer from excessive etching damage while preparing the structure for the final etching step that achieves the target depth.
3Quantity of substance
If aggressive etching is used to ensure complete conductive layer removal, then removal is thorough, but damage to the insulating layer increases
Solution Approach 1:
The etching process is divided into multiple sequential steps where each step removes a portion of the conductive layer. The first etching process removes part of the conductive layer with controlled aggression, and the second etching process removes the remainder. This segmentation ensures complete removal while distributing the damage impact across multiple controlled steps, minimizing total insulating layer damage.
Solution Approach 2:
Different etching parameters are optimized for each etching process step. The first etching process uses parameters that balance removal effectiveness with insulating layer protection. The second etching process uses adjusted parameters to complete the removal. This parameter optimization ensures thorough conductive layer removal while minimizing harmful effects on the insulating layer.
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: forming multiple trenches spaced apart from each other and extending in a first direction in a substrate, and forming a first insulating layer on sidewalls and bottoms of the trenches; forming a first conductive layer on a surface of the first insulating layer; removing part of the first conductive layer to an initial depth by a first etching process; removing remaining part of the first conductive layer to a target depth by a second etching process.