Semiconductor Trench Filling via CMP and Epitaxy
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Solution Overview
Problem
The challenge lies in forming a device isolation layer in semiconductor devices with high aspect ratio trenches, where existing methods face difficulties in filling the trenches effectively and may degrade the tunnel oxide layer due to high temperature processes, especially in multilayer structured flash memory devices.
Innovation Solution
A method involving forming trenches on a semiconductor substrate, filling them with a semiconductor layer, and then using a combination of chemical mechanical polishing (CMP) and epitaxy growth processes to create crystalline semiconductor patterns, which reduces the complexity and degradation issues associated with high aspect ratio trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a hybrid gap-fill structure with multiple layers including SOG layer and HDP layer is used to fill high aspect ratio trenches, then the trench filling difficulty is addressed, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the trench filling process into multiple stages: first forming a base insulating layer, then selectively filling remaining trenches with a second insulating layer. This segmentation allows simple process steps to achieve what would otherwise require complex hybrid structures, reducing device complexity while maintaining effective trench filling capability.
Solution Approach 2:
The patent performs preliminary planarization and selective removal of insulating layers before final trench filling. By preparing the structure in advance and removing unnecessary materials, the process avoids the need for complex hybrid gap-fill structures, simplifying the overall device architecture while ensuring proper trench filling.
2Ease of manufacture
If an annealing process at high temperature is used to form trench device isolation layer with USG layer or SOG layer, then the trench filling is achieved, but the tunnel oxide layer quality is degraded due to hot temperature stress
Solution Approach 1:
The patent changes the temperature parameter of the annealing process, performing it at a lower temperature (e.g., 400-450°C) rather than the conventional high temperature. This parameter change allows the trench device isolation layer to be formed effectively while preventing degradation of the tunnel oxide layer quality, thus resolving the contradiction between manufacturability and reliability.
3Ease of manufacture
If multiple processes are used to form trench device isolation layer, then the isolation structure is achieved, but devices formed under the top semiconductor layer are degraded
Solution Approach 1:
The patent extracts and removes unnecessary intermediate layers (such as the SOG layer) from the multi-process sequence. By eliminating redundant process steps and materials, the overall process complexity is reduced, thereby minimizing the cumulative degradation effect on devices formed under the top semiconductor layer while still achieving the required isolation structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms a device isolation layer with reduced dishing effects and maintains the quality of the tunnel oxide layer, addressing the challenges of filling high aspect ratio trenches and minimizing the impact on the multilayer structure of semiconductor devices.
Implementation Method 1
planarizing the semiconductor layer using a first planarization process
Implementation Method 2
performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer
Implementation Method 3
performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer
Data Source
AI summary
A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.