Semiconductor Trench Filling via Sacrificial Layer Void Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing semiconductor devices with a super junction structure is the difficulty in filling p-type semiconductor layers into trenches without defects, such as voids, especially when the trench depth-to-opening width ratio is large.
Innovation Solution
The method involves preparing wafers with enlarged opening portions in trenches, growing semiconductor layers under specific conditions to create spaces, and then removing the surface layer to an intermediate level to avoid void exposure, thereby preventing defects and improving manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trenches with large depth-to-opening width ratio are used to form super junction structure, then device performance is improved, but filling p-type semiconductor layers without defects becomes difficult
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial layers (oxide layers or dummy semiconductor layers) at the bottom of trenches before growing the p-type semiconductor layers. These sacrificial layers are formed in advance to prevent void formation during the subsequent epitaxial growth process, thereby ensuring defect-free filling of deep trenches while maintaining high device performance
Solution Approach 2:
The patent introduces intermediary materials (sacrificial oxide layers or dummy semiconductor layers) that mediate between the trench structure and the p-type semiconductor layers. These intermediary layers act as placeholders that prevent void formation during epitaxial growth, and are subsequently removed to achieve the desired super junction structure without defects
2Ease of manufacture
If p-type semiconductor layers are filled into deep trenches, then super junction structure is formed, but voids are generated within the filled layers
Solution Approach 1:
The sacrificial layers are formed preliminarily at the trench bottom before p-type semiconductor layer growth. This preliminary action ensures that the epitaxial growth proceeds uniformly without forming voids, as the sacrificial layers provide a foundation that prevents premature termination of crystal growth
Solution Approach 2:
The patent converts the potential harm of void formation into a benefit by using sacrificial layers that deliberately occupy the space where voids would form. These sacrificial layers are then removed, and the void space is refilled with proper semiconductor material, thereby converting the harmful void formation issue into a controlled process that ensures defect-free structures
3Productivity
If surface layer is removed to intermediate level to eliminate small voids, then manufacturing yield is improved, but processing complexity increases
Solution Approach 1:
The sacrificial layers are formed preliminarily to prevent void formation in the first place. This preliminary prevention approach reduces the need for subsequent corrective processing steps, thereby improving manufacturing yield without significantly increasing overall process complexity
Solution Approach 2:
The sacrificial layers are discarded after serving their purpose of preventing void formation during epitaxial growth. Their removal and the subsequent refilling process is a controlled operation that improves yield by eliminating defective structures, while the overall complexity is managed through systematic process integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the generation of large voids within the p-type pillars and allows for the removal of small voids, enhancing the manufacturing yield and device performance by suppressing defect formation and maintaining the integrity of the super junction structure.
Implementation Method 1
forming a first semiconductor layer of a second conductivity type inside the first trench of the first wafer under a first growth condition so that a first space remains in the first opening portion of the first trench
Implementation Method 2
removing a surface portion of the second wafer to a depth corresponding to an intermediate level between the first level and the second level, the surface layer including a portion of the third semiconductor layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes preparing a first wafer including a first trench; forming a first semiconductor layer inside the first trench so that a first space remains in the first trench; obtaining a first level corresponding to a bottom of the first space and a second level estimated by a size or a shape of the first space; preparing a second wafer including a second trench having a shape and a size substantially same as a shape and a size of the first trench; forming a second semiconductor layer inside the second trench in the second so that a second space remains in the second trench; forming a third semiconductor layer to fill the second space in the second trench; and removing a surface portion of the second wafer to a depth corresponding to a level between the first level and the second level.