Semiconductor Device Trench Gate Depth Optimization

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Solution Overview

Problem

Conventional reverse-conducting IGBTs face challenges in miniaturization and loss reduction due to insufficient breakdown tolerance and increased power loss, particularly in the diode region, which affects thermal design and reliability, and the trench structure in the diode part contributes to electric field concentration and decreased breakdown voltage.

Innovation Solution

A semiconductor device with an IGBT region and a MOSFET region, featuring a trench gate structure where the formation depth of the trench-gate adjacent region is deeper than the boundary trench gate, mitigating electric field concentration and improving breakdown voltage, and incorporating a planar gate as a field plate to enhance breakdown voltage in the MOSFET region, allowing the built-in diode to function and reducing power loss during IGBT operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the diode region is reduced to improve current density and secure IGBT region, then device miniaturization is achieved, but breakdown tolerance becomes insufficient during recovery operation

Engineering Contradiction:

Improvedevice sizeVSAvoidbreakdown tolerance

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by giving different structural characteristics to different regions: the IGBT region uses a trench gate structure optimized for low on-state loss, while the diode region uses a planar gate structure optimized for high breakdown voltage. This regional differentiation allows each part to be optimized for its specific function without compromising the other.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the device into distinct IGBT region and diode region with different gate structures. The trench gate is selectively formed in the IGBT region while the planar gate is formed in the diode region, allowing independent optimization of each region's characteristics.

Inventive Principle:

Principle #1Segmentation

2Loss of energy

If the P layer with trench structure is formed in the diode part to reduce steady loss, then steady loss during diode operation is reduced, but electric field concentration occurs causing decreased breakdown voltage

Engineering Contradiction:

Improvesteady lossVSAvoidbreakdown voltage

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Instead of using the trench gate structure in the diode region as done in conventional designs, the patent inverts the approach by using a planar gate structure in the diode region. This inversion resolves the contradiction by prioritizing breakdown voltage over steady loss reduction in the diode region.

Inventive Principle:

Principle #13The other way round (Inversion)

3Speed

If lifetime control by heavy metal diffusion or charged particle beam is performed to speed up recovery characteristics, then recovery speed is improved, but surge voltage is generated reducing safe operating area

Engineering Contradiction:

Improverecovery speedVSAvoidsafe operating area

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent converts the harmful effect of electric field concentration (which normally reduces breakdown voltage) into a beneficial field distribution pattern. The planar gate structure in the diode region creates a more uniform electric field that extends the safe operating area, while still achieving fast recovery through optimized doping profiles without requiring heavy metal diffusion.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11251177B2Semiconductor device

Publication Date: 2022.02.15 MITSUBISHI ELECTRIC CORP

AI summary

A semiconductor device 1 has an IGBT region and a MOSFET region. A plurality of channel doped P layers formed in the MOSFET region include a trench-adjacent channel doped P layer whose side surface is in contact with a boundary trench gate formed between the IGBT region and the MOSFET region. A formation depth of the trench-adjacent channel doped P layer is set deeper than a formation depth of the boundary trench gate. In the MOSFET region, an N type MOSFET having a planar structure is configured including a channel region in the channel doped P layer, a gate insulating film in an interlayer oxide film, and a gate polysilicon serving as a planar gate.