Semiconductor Trench Gate Doped Layer GIDL Reduction
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Solution Overview
Problem
The rapid miniaturization of semiconductor devices leads to increased Gate-Induced-Drain-Leakage (GIDL) current due to the proportional reduction in device size without corresponding voltage reduction, affecting device reliability.
Innovation Solution
A semiconductor structure with a doped layer comprising a transition layer and an ion implantation layer is formed, where the transition layer is located below the ion implantation layer, and the gate is positioned within a trench such that the top surface of the transition layer is not lower than the bottom surface of the gate, reducing the overlapping area and local electric fields between the gate and source/drain areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the semiconductor device is reduced, then the integration density is improved, but the GIDL current increases due to the strong electric field effect in short channel devices
Solution Approach 1:
The doped layer is segmented into two distinct regions: a transition layer with lower doping concentration and an ion implantation layer with higher doping concentration. This segmentation allows the device to maintain high integration density while reducing GIDL current by creating a graded doping profile that mitigates the strong electric field effect in short channel devices.
Solution Approach 2:
Different regions of the doped layer are assigned different doping concentrations to address local electrical characteristics. The transition layer with lower doping concentration is positioned where the electric field is strongest (near the gate bottom), while the ion implantation layer with higher doping concentration is positioned deeper in the substrate, creating a locally optimized doping profile that reduces GIDL current while maintaining overall device performance.
2Length of moving object
If the gate oxide layer thickness is reduced to 2 nm or smaller, then the device size is reduced, but the GIDL current effect becomes very strong affecting device reliability
Solution Approach 1:
The doping concentration parameter is changed across different regions of the doped layer. By implementing a graded doping profile with lower concentration in the transition layer and higher concentration in the ion implantation layer, the electric field distribution is modified to reduce GIDL current effect, thereby improving device reliability while maintaining thin gate oxide layer dimensions.
3Object-generated harmful factors
If the overlapping area between the gate and source/drain areas is reduced, then the GIDL current is reduced, but the device area increases
Solution Approach 1:
The solution moves from a two-dimensional view of overlapping area to a three-dimensional doping profile approach. By controlling the vertical distribution of doping concentrations (transition layer and ion implantation layer at different depths), the patent reduces GIDL current through the graded profile effect while maintaining a compact planar device footprint, effectively utilizing the depth dimension to solve the leakage problem without increasing surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces GIDL current by minimizing current leakage between the gate and source/drain areas, thereby enhancing the reliability and data storage time of semiconductor devices.
Implementation Method 1
a doped layer is formed in a semiconductor substrate. The doped layer includes a transition layer and an ion implantation layer located on the transition layer
Data Source
AI summary
A semiconductor structure includes: a semiconductor substrate, in which a trench is provided in the semiconductor substrate, and a gate is formed in the trench; and a doped layer, in which the doped layer is located in the semiconductor substrate on an outer side of the trench. In a direction perpendicular to the semiconductor substrate, the doped layer includes a transition layer and an ion implantation layer located on the transition layer. A doping concentration of the transition layer is less than a doping concentration of the ion implantation layer; and in the direction perpendicular to the semiconductor substrate, a top surface of the transition layer is not lower than a bottom surface of the gate.