Semiconductor Device Trench Gate Layout Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with trench gate structures experience imbalance in gate charge during switching operations due to irregular spacing of trench sections, leading to inefficiencies in gate charge Qg values.
Innovation Solution
The semiconductor device incorporates a design with evenly spaced gate trench sections and emitter trench sections arranged in loop-shape structures, where emitter trench sections are positioned between adjacent gate trench sections, and both types of trench sections are formed at constant intervals to reduce electric field concentration and improve breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of emitter trench sections is increased to reduce gate charge Qg value, then gate charge Qg is reduced, but imbalance during switching operation occurs
Solution Approach 1:
The gate trench sections are divided into multiple segments with constant intervals, and emitter trench sections are selectively positioned in specific regions between adjacent gate trench sections. This segmentation approach allows reduction of gate charge while maintaining balanced switching operation by ensuring uniform electrical characteristics across different regions.
Solution Approach 2:
Emitter trench sections are not uniformly distributed but are selectively positioned in specific regions between gate trench sections. This local quality approach optimizes the distribution of emitter trench sections to achieve both reduced gate charge and balanced switching performance by addressing regional variations in electrical characteristics.
2Ease of manufacture
If trench sections are arranged at irregular intervals, then manufacturing flexibility is improved, but electric field concentration increases and breakdown voltage decreases
Solution Approach 1:
Gate trench sections are arranged at constant intervals to create equipotential regions, which uniformizes the electric field distribution across the device. This arrangement prevents electric field concentration at irregular intervals while maintaining manufacturing flexibility through the systematic positioning of emitter trench sections in designated regions.
Data Source
AI summary
Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of gate trench sections formed in the semiconductor substrate; and a plurality of emitter trench sections formed in the semiconductor substrate, one or more emitter trench sections provided in each region between adjacent gate trench sections of the plurality of gate trench sections, wherein the semiconductor device includes at least one of: pairs of gate trench sections in which at least two gate trench sections of the plurality of gate trench sections are connected; and a pair of emitter trench sections in which at least two emitter trench sections of the plurality of emitter trench sections are connected.