Semiconductor Device Trench Gate Shield Integration

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Solution Overview

Problem

Conventional semiconductor devices with polysilicon shield layers require complex patterning procedures and large die sizes due to the need for connecting polysilicon gate and shield layers, leading to increased gate-drain parasitic capacitance and manufacturing complexity.

Innovation Solution

A semiconductor device design where the source interconnect layer protrudes from the upper end of a trench, allowing the gate electrode to be buried within trenches without extending outside, thereby simplifying the manufacturing process and reducing the number of necessary procedures, and eliminating the need for outer peripheral connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polysilicon shield layer is provided below polysilicon gate electrode, then gate-drain parasitic capacitance is reduced and switching characteristics are improved, but patterning procedures become complex and die size increases

Engineering Contradiction:

Improveswitching characteristicsVSAvoidpatterning procedures

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the gate electrode and shield layer into a single integrated structure formed by one patterning process. The gate electrode is formed with a specific profile that inherently provides the shielding function, eliminating the need for separate shield layer patterning and reducing overall device complexity while maintaining the gate-drain capacitance reduction benefit.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The gate electrode structure is designed to serve dual functions: as the primary gate control electrode and as the shield layer. By making the gate electrode itself provide the shielding effect through its geometric configuration and positioning, the invention eliminates redundant structures and simplifies the manufacturing process while achieving both gate control and parasitic capacitance reduction.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If polysilicon shield layer is connected to source electrode at outer peripheral portion, then gate-drain parasitic capacitance is reduced, but die size becomes large

Engineering Contradiction:

Improvegate-drain parasitic capacitance reductionVSAvoiddie size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar connection at the outer periphery to a vertical integration within the trench structure. The gate electrode is positioned and configured within the trench to provide shielding in the vertical dimension, eliminating the need for horizontal extension to the outer periphery and reducing the required die area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The shield function is nested within the gate electrode structure itself rather than being a separate external component. The gate electrode is configured to provide both gate control and shielding functions in a nested arrangement, eliminating the need for separate shield layer and its external connection, thereby reducing die size.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Manufacturing precision

If separate patterning procedures are used for polysilicon gate electrode and polysilicon shield layer, then precise control is achieved, but manufacturing complexity increases

Engineering Contradiction:

Improvepositioning precisionVSAvoidmanufacturing process

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent combines the patterning of the gate electrode and shield layer into a single patterning step. The gate electrode is formed with a specific profile that inherently defines both the gate structure and the shielding region, eliminating multiple patterning procedures while maintaining precise positioning through the unified pattern formation process.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8748261B2Method of manufacturing semiconductor device, and semiconductor device

Publication Date: 2014.06.10 RENESAS ELECTRONICS CORP

AI summary

A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.